12-8
GTL+ INTERFACE SPECIFICATION
ρ
&
δ
are respectively, the amplitude and duration of square-wave ringback, below the threshold
voltage (V
REF
), that the receiver can tolerate without increasing T
SU
by more than 0.05 ns for a
given pair of (
α
,
τ
) values.
If, for any reason, the receiver cannot tolerate any ringback across the reference threshold
(V
REF
), then
ρ
would be a negative number, and
δ
may be infinite. Otherwise, expect an inverse
(or near-inverse) relationship between
ρ
and
δ
, where the more the ringback, the shorter is the
time that the ringback is allowed to last without causing the receiver to detect it.
φ
is the final minimum settling voltage, relative to the reference threshold (V
REF
), that the input
should return to after ringback to guarantee a valid logic state at the internal flip-flop input.
φ
is a function of the input amplifier gain, its differential mode offset, and its intrinsic maximum
level of differential noise.
Specifying the values of
α, τ, ρ, δ
, and
φ
is the responsibility of the receiver vendor. The system
designer should guarantee that all signals arriving at such a receiver remain in the permissible
region specified by the vendor parameters as they correspond to those of the idealized square
waves of Figure 12-3 and Figure 12-4. For instance, a signal with ringback inside the box delin-
eated by
ρ
and
δ
can have a
τ
equal to or longer than the minimum, and an
α
equal to or larger
than the minimum also.
A receiver that does not tolerate any ringback would show the following values for the above
parameters:
α
> 0V,
τ
> Tsu,
ρ
= -200 mV,
δ
= undefined,
φ
= 200 mV.
A receiver which tolerates 50 mV of ringback would show the following values for the above
parameters:
α
> 0V,
τ
= data sheet,
ρ
= -150 mV,
δ
= data sheet,
φ
> tens of mV (data sheet).
Finally, a receiver which tolerates ringback across the switching threshold would show the fol-
lowing values for the above parameters:
α
> 0 V,
τ
= data sheet,
ρ
> 0 mV (data sheet),
δ
= data sheet,
φ
> tens of mV.
where
δ
would usually be a brief amount of time, yielding a pulse (or “blip”) beyond V
REF
.
12.1.4.
AC Parameters: Flight Time
Signal Propagation Delay is the time between when a signal appears at a driver pin and the time
it arrives at a receiver pin. Flight Time is often used interchangeably with Signal Propagation
Delay but it is actually quite different. Flight time is a term in the timing equation that includes
the signal propagation delay, any effects the system has on the T
CO
of the driver, plus any
adjustments to the signal at the receiver needed to guarantee the T
SU
of the receiver. More pre-
cisely, Flight Time is defined to be:
Summary of Contents for Pentium Pro Family
Page 17: ...1 Component Introduction ...
Page 26: ...2 Pentium Pro Processor Architecture Overview ...
Page 27: ......
Page 36: ...3 Bus Overview ...
Page 62: ...4 Bus Protocol ...
Page 105: ...5 Bus Transactions and Operations ...
Page 126: ...6 Range Registers ...
Page 131: ...7 Cache Protocol ...
Page 135: ...8 Data Integrity ...
Page 148: ...9 Configuration ...
Page 161: ...10 Pentium Pro Processor Test Access Port TAP ...
Page 172: ...11 Electrical Specifications ...
Page 201: ...12 GTL Interface Specification ...
Page 229: ...13 3 3V Tolerant Signal Quality Specifications ...
Page 233: ...14 Thermal Specifications ...
Page 239: ...15 Mechanical Specifications ...
Page 241: ...15 2 MECHANICAL SPECIFICATIONS s Figure 15 1 Package Dimensions Bottom View ...
Page 252: ...16 Tools ...
Page 260: ...16 8 TOOLS Figure 16 4 Generic MP System Layout for Debug Port Connection ...
Page 264: ...17 OverDrive Processor Socket Specification ...
Page 290: ...A Signals Reference ...
Page 320: ...Index ...
Page 328: ......