Platform Management
Intel® Server Boards SE7320SP2 and SE7525GP2
Revision
4.0
114
5.3.1.1 Power-up
Sequence
When turning on the system power in response to one of the event occurrences listed in
Table 53 below, the mBMC executes the following procedure:
The mBMC asserts
Power On
and waits for the power subsystem to assert
Power Good
.
The system is held in reset.
The mBMC sends a
Set ACPI Power State
command, indicating an S0 state to all
management controllers whose SDR management device records indicate that they
should receive the notification.
The mBMC initializes all sensors to their
Power On
initialization state. The Init Agent is
run.
The mBMC attempts to boot the system by running the FRB algorithm.
5.3.1.2 Power-down
Sequence
To power down the system, the mBMC effectively performs the sequence of power-up steps in
reverse order. This operation can be initiated by one of the event occurrences listed in Table 53
and proceeds as follows:
The mBMC asserts system reset (de-asserts
Power Good
).
If enabled, the mBMC sends a
Set ACPI Power State
command, indicating an S0 state
to all management controllers whose SDR management device records indicate that
they should receive the notification.
The mBMC de-asserts the
Power On
signal.
The power subsystem turns off system power upon de-assertion of the
Power On
signal.
5.3.1.3
Power Control Sources
The sources listed in the following table can initiate power-up and/or power-down activity.
Table 53. Power Control Initiators
#
Source
External Signal Name or
Internal Subsystem
Capabilities
1
Power Button
FP Power button
Turns power on or off
2
mBMC Watchdog Timer
Internal mBMC timer
Turns power off, or power cycle
3
Platform Event Filtering
PEF
Turns power off, or power cycle
4
Command
Routed through command processor
Turns power on or off, or power cycle
5
Power state retention
Implemented via mBMC internal logic
Turns power on when AC power returns
6
Chipset
Sleep S5
Turns power on or off
Summary of Contents for SE7320SP2 - 800MHZ Ecc Ddr Xeon
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