Intel® Server Board SE7520BD2 Technical Product Specification
Product Overview
Revision 1.3
Intel Confidential
19
In the “Mirrored” operating state, the occurrence of correctable and uncorrectable ECC errors
are tracked and logged normally by the MCH, and escalated to system interrupt events as
specified by the configuration register settings associated with errors on the memory
subsystem. Counters implementing the “leaky bucket” function just described for on-line DIMM
sparing track the aggregate count of single-bit and multiple-bit errors on a per DIMM basis.
2.8.5 I
2
C Bus Detail
The I
2
C bus is used by the system BIOS to retrieve DIMM information needed to program the
MCH memory registers, which are required to boot the system.
The following table provides the I
2
C addresses for each DIMM slot.
Table 5. I
2
C Addresses for Memory Module SMB
Device
Address
DIMM 3B
0xA8
DIMM 3A
0xA0
DIMM 2B
0xAA
DIMM 2A
0xA2
DIMM 1B
0xAC
DIMM 1A
0xA4
2.9 PCI Sub-System Detail
2.9.1 ICH5-R
PCI
Interface
The Intel® 8280 ER I/O Controller Hub (ICH5-R) PCI interface is a multi-function device
providing an upstream hub interface for access to several embedded I/O functions and features
including:
•
PCI Local Bus Specification, Revision 2.3 with support for 33-MHz PCI operations.
•
ACPI power management logic support
•
Enhanced DMA controller, interrupt controller, and timer functions
•
Integrated IDE controller supports Ultra ATA100/66/33
•
Integrated SATA controller
•
USB host interface with support for eight USB ports; four UHCI host controllers; one
EHCI high-speed USB 2.0 host controller
•
Integrated LAN controller
•
Integrated ASF controller
•
System Management Bus (SMBus) Specification, Version 2.0 with additional support for
I
2
C devices
•
Low Pin Count (LPC) interface
•
Firmware Hub (FWH) interface support
Each function within the ICH5-R has its own set of configuration registers. Once configured,
each appears to the system as a distinct hardware controller sharing the same PCI bus
interface.
