Intel® SHG2 DP Server Board Technical Product Specification
Processor and Chipset
Revision 1.0
Intel Order Number C11343-001
7
be applied to the system unless primary slot is populated with a processor, unless used in fault
resilient booting (FRB) mode (details in Section 5).
When using two processors, notice that the processor pins are physically 180 degrees out-of-
phase. Improper processor installation may permanently damage processor pins.
2.2.1
Processor Bus Termination/Regulation/Power
The termination circuitry required by the Intel Xeon processor bus (AGTL+) signaling
environment, and the circuitry to set the AGTL+ reference voltage, are implemented directly on
the processors. The baseboard provides 1.5 V AGTL+ termination power (VTT), and VRM 9.1-
compliant DC-to-DC converters to provide processor power (VCC_P) at each socket. The
baseboard provides two embedded VRMs to power the processors, which derive power from
the +5 V and 12 V supplies. Both processors share the same VRM to power their core.
2.2.2
Miscellaneous Processor Subsystem Logic
In addition to the circuitry described above, the processor subsystem contains the following:
•
Reset configuration logic.
•
Processor presence detection circuitry.
•
Server management registers and sensors.
2.2.2.1
Reset Configuration Logic
On the SHG2 platform, the BMC is responsible for configuring the processor speeds. The BMC
uses the processor speed information (derived from the Intel Xeon processor SECC FRU
devices) to determine the appropriate speed to program into the speed-setting device (I
2
C-
based EEPROM Mux).
The processor information is read at every system power-on. The EEMUX is set to correspond
to the speed of the slowest processor.
2.2.2.2
Processor Presence Detection
Logic is provided on the baseboard to detect the presence and identity a properly installed
processor. This prevents system power on if an empty socket in the primary section is detected
in the primary processor socket (labeled Proc1, located closest to the edge of the server
board), thus preventing operation of the system with an improperly terminated AGTL+
processor bus. The BMC checks this logic and will not turn on the system DC power until the
bus is terminated properly with a processor in the primary socket.
2.2.2.3 APIC
Bus
Interrupt notification and generation for the processors is done using a front side bus (FSB)
between local APIC, in each processor, and the I/O APIC in the CSB5 located on the
baseboard.
2.2.3
Server Management Registers and Sensors
The BMC manages registers and sensors associated with the processor/memory subsystem.
