Midplane Board
Intel
®
Carrier Grade Server TIGPT1U TPS
Revision
1.0
54
7.3.2 SCSI
Bus
The midplane system board SCSI subsystem passes the SCSI bus from the SE7210TP1-E
System Baseboard to the internal SCSI drives. The SCSI bus is Ultra 320 (SPI-4) capable.
Single-Ended (SE) drives are not supported. SE drives should not be installed as the behavior
of the drives is unpredictable and data corruption could result. The bus is comprised of 68
signals. The bus clock is 80 MHz. The 320 Mbytes data rate results from double transition (DT)
data transfers on a two byte wide bus. The SCSI bus attaches to the SE7210TP1-E System
Baseboard via a 68-pin SCSI connector.
320 Mbytes/s = 2 byte bus * 80 MHz clock * double transitions.
NOTE:
The SCSI drives and SCSI controller on the SE7210TP1-E System Baseboard
determine actual SCSI bus data rate.
7.3.3
SCA2 Connector Interlocks
The SCA2 connectors on the Midplane board (MPB) have interlocks. The mated1 and mated2
signals are used to provide Interlock notification for the SCSI device and Baseboard,
respectively. Sensing and delay circuitry on the MPB will utilize the input mating signal from the
drive to monitor hot insertion. Approximately 60 mS after hot insertion, the MPB activates its
own mated acknowledgement signal to the drive to notify the drive that it can safely power-up.
7.3.4 Signal
Descriptions
The following notations are used to describe the signal type, from the perspective of the FPIO
SCSI subsystem:
Notation Description
I
Input pin to the SCSI subsystem
O
Output pin from the SCSI subsystem
I/O Bi-directional
(input/output) pin
PWR Power
Supply
pin
The signal description also includes the type of buffer used for the particular signal:
Notation Description
LVD
Low Voltage Differential SCSI
SE
Standard Single Ended SCSI
TTL
5 V TTL signals
CMOS
5 V CMOS signals
3.3 V CMOS
3.3 V CMOS signals
Analog
Typically a voltage reference or specialty power supply