Developer’s Manual
January, 2004
169
Intel XScale® Core
Developer’s Manual
Performance Considerations
UMULL
Rs[31:15] = 0x00000
0
1
RdLo = 2; RdHi = 3
2
1
3
3
3
Rs[31:27] = 0x00
0
1
RdLo = 3; RdHi = 4
3
1
4
4
4
all others
0
1
RdLo = 4; RdHi = 5
4
1
5
5
5
a.
If the next instruction needs to use the result of the multiply for a shift by immediate or as Rn in a QDADD or QDSUB, one
extra cycle of result latency is added to the number listed.
Table 10-7.
Multiply Implicit Accumulate Instruction Timings
Mnemonic
Rs Value (Early
Termination)
Minimum Issue
Latency
Minimum Result
Latency
Minimum Resource
Latency
(Throughput)
MIA
Rs[31:15] = 0x0000
or
Rs[31:15] = 0xFFFF
1
1
1
Rs[31:27] = 0x0
or
Rs[31:27] = 0xF
1
2
2
all others
1
3
3
MIAxy
N/A
1
1
1
MIAPH
N/A
1
2
2
Table 10-8.
Implicit Accumulator Access Instruction Timings
Mnemonic
Minimum Issue Latency
Minimum Result Latency
Minimum Resource Latency
(Throughput)
MAR
2
2
2
MRA
1
(RdLo = 2; RdHi = 3)
a
a.
If the next instruction needs to use the result of the MRA for a shift by immediate or as Rn in a QDADD or QDSUB, one extra
cycle of result latency is added to the number listed.
2
Table 10-6.
Multiply Instruction Timings (Sheet 2 of 2)
Mnemonic
Rs Value
(Early Termination)
S-Bit
Value
Minimum
Issue Latency
Minimum Result
Latency
a
Minimum Resource
Latency (Throughput)