18
January, 2004
Developer’s Manual
Intel XScale® Core
Developer’s Manual
Introduction
1.2.2.6
Performance Monitoring
Performance monitoring counters have been added to the Intel XScale
®
core that can be configured
to monitor various events in the core. These events allow a software developer to measure cache
efficiency, detect system bottlenecks and reduce the overall latency of programs.
Chapter 8, “Performance Monitoring”
discusses this in more detail.
1.2.2.7
Power Management
The Intel XScale
®
core incorporates a power and clock management unit that can assist ASSPs in
controlling their clocking and managing their power. These features are described in
Section 7.3,
“CP14 Registers” on page 7-96
.
1.2.2.8
Debug
The Intel XScale
®
core supports software debugging through two instruction address breakpoint
registers, one data-address breakpoint register, one data-address/mask breakpoint register, and a
trace buffer.
Chapter 9, “Software Debug”
discusses this in more detail.
1.2.2.9
JTAG
Testability is supported on the Intel XScale
®
core through the Test Access Port (TAP) Controller
implementation, which is based on IEEE 1149.1 (JTAG) Standard Test Access Port and
Boundary-Scan Architecture. The purpose of the TAP controller is to support test logic internal and
external to the core such as built-in self-test and boundary-scan.
Appendix B
discusses this in more detail.