Developer’s Manual
January, 2004
3
Intel XScale® Core
Developer’s Manual
Contents
Contents
1
Introduction .................................................................................................................................... 13
1.1
About This Document ......................................................................................................... 13
1.1.1
How to Read This Document ................................................................................. 13
1.1.2
Other Relevant Documents ................................................................................... 14
1.2
High-Level Overview of the Intel XScale
®
Core..................................................................15
1.2.1
ARM Compatibility .................................................................................................15
1.2.2
Features................................................................................................................. 16
1.2.2.1
Multiply/Accumulate (MAC).................................................................... 16
1.2.2.2
Memory Management ............................................................................ 17
1.2.2.3
Instruction Cache ................................................................................... 17
1.2.2.4
Branch Target Buffer..............................................................................17
1.2.2.5
Data Cache ............................................................................................17
1.2.2.6
Performance Monitoring.........................................................................18
1.2.2.7
Power Management ............................................................................... 18
1.2.2.8
Debug .................................................................................................... 18
1.2.2.9
JTAG ...................................................................................................... 18
1.3
Terminology and Conventions ............................................................................................19
1.3.1
Number Representation......................................................................................... 19
1.3.2
Terminology and Acronyms ................................................................................... 19
2
Programming Model ......................................................................................................................21
2.1
ARM Architecture Compatibility ..........................................................................................21
2.2
ARM Architecture Implementation Options.........................................................................21
2.2.1
Big Endian versus Little Endian ............................................................................. 21
2.2.2
26-Bit Architecture .................................................................................................21
2.2.3
Thumb....................................................................................................................21
2.2.4
ARM DSP-Enhanced Instruction Set ..................................................................... 22
2.2.5
Base Register Update............................................................................................22
2.3
Extensions to ARM Architecture ......................................................................................... 23
2.3.1
DSP Coprocessor 0 (CP0).....................................................................................23
2.3.1.1
Multiply With Internal Accumulate Format .............................................24
2.3.1.2
Internal Accumulator Access Format ..................................................... 27
2.3.2
New Page Attributes .............................................................................................. 29
2.3.3
Additions to CP15 Functionality ............................................................................. 31
2.3.4
Event Architecture .................................................................................................32
2.3.4.1
Exception Summary ............................................................................... 32
2.3.4.2
Event Priority..........................................................................................32
2.3.4.3
Prefetch Aborts ...................................................................................... 33
2.3.4.4
Data Aborts ............................................................................................34
2.3.4.5
Events from Preload Instructions ...........................................................35
2.3.4.6
Debug Events ........................................................................................ 36
3
Memory Management....................................................................................................................37
3.1
Overview ............................................................................................................................. 37
3.2
Architecture Model .............................................................................................................. 38
3.2.1
Version 4 vs. Version 5 ..........................................................................................38
3.2.2
Memory Attributes.................................................................................................. 38
3.2.2.1
Page (P) Attribute Bit ............................................................................. 38