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Application Note 1662

ISL97682 LED Driver Evaluation Board User Manual

Introduction

The ISL97682IRTZEVALZ Evaluation Board provides a 
complete testing platform for the ISL97682, a two channel 
LED driver. Please refer to the product datasheet (ISL97682, 

FN7689

) for detailed information including pinout, pin function 

description, electrical specifications, applications related 
information, etc.

Instructions

Please follow the steps described below to start your 
evaluation.

1. For both switch #1 and #2 (SW1 and SW2 shown on the 

board), set them to position 3 (left side).

2. For enable control jumper JP1, put the shunt to the “ON” 

position (right side) to connect EN pin to VIN. When the 
shunt is set to the “OFF” position, it will disable the chip by 
pulling the EN pin to ground.

3. Connect JP14 so the VIN pin is connected to PVIN.
4. For JP20, connect the shunt to the upper position.
5. Connect WR and JP2-JP6.
6. Apply 1.5V~5.5V PWM signal between PWMI pin and 

AGND.

7. Apply 4V~26.5V between PVIN and PGND and the LEDs 

should be lit, and you can start the evaluation.

NOTE: In step #1 above, the SW1, SW2 position can be adjusted to 
different positions for different configurations, see Table 1 for details.

• The LED maximum DC current adjustment.

For each channel, the maximum DC current is set by 
resistance connected to RSET pin. The current for each 
channel can be calculated as shown in Equation 1:

On the board, a potentiometer R5 and a few other resistors 
are provided for easily adjust the LED maximum DC current. 

Please refer to the “ISL97682IRTZEVALZ Evaluation Board 
Schematic” on page 2 
for more details.

• LED dimming frequency and duty cycle.

- As mentioned in step #4 above, when the shunt on JP20 

is connected to the upper position, FPWM/DPWM pin is 
connected to VDC, the device enters direct PWM mode, 
which means both the LED dimming frequency and the 
duty cycle are synchronized with the external PWM signal 
applied on the PWMI pin.

- When the shunt on JP20 is connected to the lower 

position, the FPWM/DPWM pin is connected to a resistor. 
Under such conditions, the LED dimming frequency of the 
chip is programmed by the resistance connected on the 
FPWM/DPWM pin as per Equation 2:

The duty cycle is still modulated by the external PWM 
signal applied on PWMI pin. On board, potentiometer R11 
and a few other resistors are provided for easily adjusting 
the LED dimming frequency under such a configuration.

TABLE 1.

SW1

POSITION

SW2

POSITION

DESCRIPTION

1

1

LX switching frequency = 600kHz, PFM 
CH1 and CH3

3

3

LX switching frequency = 1MHz, PFM 
CH1 and CH3

3

1

LX switching frequency = 600kHz, No PFM 
CH1 and CH3

1

3

LX switching frequency = 1MHz, No PFM 
CH1 and CH3

(EQ. 1)

I_LED mA

(

)

402

RSET k

Ω

(

)

----------------------------

=

(EQ. 2)

FPWM Hz

(

)

12.4

10

7

R_FPWM

Ω

( )

-----------------------------------

=

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

|

Copyright Intersil Americas Inc. 2011. All Rights Reserved.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

October 11, 2011
AN1662.0

Summary of Contents for ISL97682IRTZEVALZ

Page 1: ...e provided for easily adjust the LED maximum DC current Please refer to the ISL97682IRTZEVALZ Evaluation Board Schematic on page 2 for more details LED dimming frequency and duty cycle As mentioned in step 4 above when the shunt on JP20 is connected to the upper position FPWM DPWM pin is connected to VDC the device enters direct PWM mode which means both the LED dimming frequency and the duty cycl...

Page 2: ...R9 10k C15 8 2nF C3 33pF TP1 LX TP2 VOUT TP3 CH1 TP5 CH3 VDC P5 AGND P6 AGND P7 AGND P8 AGND P9 PGND P10 PGND 2 layer board Connect top layer PGND and bottom layer AGND F1 2A Fuse JP14 R11 100k R10 0 R13 Open R12 27k JP15 JP17 EN can be connected in the following ways to enable disable the device 1 Connected it to VIN directly on JP1 to enable 2 Connected it to GND directly on JP1 to disable 3 Dir...

Page 3: ...Application Note 1662 3 AN1662 0 October 11 2011 PCB Layout FIGURE 1 TOP SILKSCREEN LAYER TOP LAYER ...

Page 4: ...Application Note 1662 4 AN1662 0 October 11 2011 FIGURE 2 BOTTOM LAYER PCB Layout Continued ...

Page 5: ...capacitors C2 0 1µF 50V 603 C3 33pF 603 C4 1µF 16V 603 C5 4 7µF 50V 1210 Murata GRM32ER71H475KA88L C6 4 7µF 50V 1210 C7 Place Holder 1210 Not Populated C8 Place Holder 1210 C9 100pF 50V 603 General purpose Ceramic X5R X7R capacitors C10 3 3nF 50V 603 C11 1nF 50V 603 C12 Place Holder 603 C13 1nF 50V 603 C14 Place Holder 603 C15 8 2nF 603 F1 2A Fuse 1206 Bel Fuse Inc C1Q 2 U1 QFN16 3MM Intersil ISL9...

Page 6: ... TEST POINT Keystone Electronics 5010 TP2 VOUT TEST POINT TP3 CH1 TEST POINT TP4 CH2 TEST POINT TP5 CH3 TEST POINT TP6 CH4 TEST POINT TP7 VDC TEST POINT TP8 RSET TEST POINT TP9 FSW PHS TEST POINT P5 AGND TEST POINT Keystone Electronics 5011 P6 AGND TEST POINT P9 PGND TEST POINT P1 PVIN POWERPOST Mill Max 3156 1 00 00 00 00 08 0 P2 VIN POWERPOST P3 EN POWERPOST P4 PWMI POWERPOST P7 AGND POWERPOST P...

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