SECTION 1: THEORY OF OPERATION
369548.DOC
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9
Analog Modulation
(refer to schematic on page 52)
This section displays the analog modulation circuitry. Incoming modem audio from the System Controller
Board appears at TXMOD, and is buffered by op amp U3A. If an external modulation source (modem or
amplified microphone) is connected to the base station’s DB9 connector, audio appears at EXTMOD.
From there the audio passes through low pass Bessel filter U2. The audio is inverted and amplified by an
op amp (U3B). It then passes on to the VCO module via VCOMOD. Pot R11 adjusts the level to suit the
VCO.
The 10 MHz reference is also modulated in order to counteract the corrective effects of the synthesizer
loop circuitry. For example, if only the VCO were modulated, the synthesizer would try to compensate for
the frequency “error,” caused by the modulation. This effectively reduces the amount of modulation
available. Modulating the reference
and
the VCO simultaneously deceives the loop into not
compensating for the modulation, because when the reference frequency goes high, the VCO frequency
goes high, and vice-versa.
An op amp (U1A) amplifies the AUDIO output from another op amp (U3D) and applies it to jumper block
JP1. Pot R4 adjusts the gain of U1A. Op amp (U1B) inverts the phase of the audio and applies it to the
other side of jumper block JP1. The purpose of the jumper block is to select the proper phase of the
audio. If the wrong phase is used, on modulation peaks the reference will swing in the same direction as
the VCO, canceling out most of the modulation. The output from the jumper block goes to the 10 MHz
reference via REFMOD.
The VBIAS input is a 2.5-volt DC source, which biases the op amps to the correct operating point. It is
generated by modem chip (U14) on the System Controller Board.
Phase Locked Loop
(refer to schematic on page 53)
This section displays phase locked loop (PLL) circuitry. The 10-MHz reference (Y1), runs synthesizer
(U6), which in turn controls VCO VCO1. The main section of this board is the synthesizer chip (U6). The
device contains the key components of a PLL, including a 1.1 GHz prescaler, programmable divider, and
phase detector.
In operation, the desired frequency is loaded into U6 as a clocked serial bit stream via the CLK and DATA
inputs. The lock detection circuitry consists of inverters U4D, diode CR1, and resistor R28. When the
synthesizer is in lock, the LD pin on U6 is high, making the EXCLD output on terminal block (TB1) high.
The EXCLD output on TB1 routes the lock detect output from the Exciter Board. This configuration tells
the CPU on the System Controller Board that it is acceptable to process received data, or to key the
transmitter when LD is high. Otherwise, if a fault in either synthesizer prevents a lock, receive and
transmit operation will be inhibited.
The switch (JP1) is used to select the supply voltage to chip U6. The UHF injection signal is generated
by module VCO1. This device is a wide-range voltage controlled oscillator (VCO). A voltage on the VT
input determines the VCO frequency. The voltage is generated by the phase detector output (PD/O) of
U2, which drives a loop filter consisting of R31, C50, C28, and C25. The filter integrates the pulses,
which normally appear on PDOUT into a smooth DC control signal for the VCO. The output of VCO1 is
attenuated by module AT1, resulting in improved VCO stability.
RF amplifier U8 amplifies the signal and applies it to a two-way power splitter (U7). One output of U7 is
connected to a switch (U5). U5 is enabled by signal TX when the transmitter is enabled. The other
output of the splitter provides feedback to U6.
