SECTION 1: THEORY OF OPERATION
369548.DOC
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IP8B Base Station Section Descriptions
System Controller
(refer to schematic on page 26)
This section displays the Central Processing Unit (CPU)(U1), clock, and power-on reset circuitry. It
provides more processing power than required for future capabilities to be incorporated without changing
processors. Such capabilities include data encryption/decryption (DES) and remote fault monitoring. U1
features a 16-bit address bus and 128K of internal flash random access memory (RAM).
NOTE:
To enter the programming mode it is necessary to reset the switch (S1) and power up again.
CPU operations are controlled by Y3 an 18.432 MHz clock module. Capacitor (C1) and an internal
Schmidt trigger circuit inside of U1 generates the power on reset signal. The RESET* output from U1
drives a latch and decoder found elsewhere on the board.
This section displays the RAM, decoder, EEPROM, and programming power supply circuitry. U2 is a
512K x 8 bit static RAM chip, which provides temporary storage of base station configuration data while
the power is on. This is necessary in order to program the base station. U2 is controlled directly by the
address, data, and control busses from the CPU.
Chip U5 decodes the A11-A14 address bus to provide chip selects for the modem and EEPROM
memory. Chip U6 is an 8-bit latch. It latches inputs from the D0-D7 bus and lights the front panel status
indicators (
TX, CD, RX1, RX2, and RX3
).
Chip U3 is a serial EEPROM, which provides 2K bits of pre-programmed data storage for the CPU. Data
is clocked out of U3 by EECLK, and back into the CPU via EEDATA.
A programming power supply is required for the flash RAM inside of the CPU, and this function is
performed by U4. This chip is a low dropout voltage regulator with a shutdown control. Resistors R22
and R21 set the output voltage. When the base station configuration data is to be stored in flash RAM,
the CPU makes VPP_ENABLE high. This turns on the regulator, producing a 12-volt output via VPP for
the flash RAM.
This section displays a dedicated processor and voltage regulator. Chip U7 is a processor, which permits
manual keyboard operation of the base station. Regulator VR2 provides 5 volts DC power for all logic
circuitry on the System Controller Board.
Input/Output
(refer to schematic on page 30)
This section displays the CPU input/output circuitry. Chip U8 is an RS232 transceiver, which interfaces
the CPU to the modem via J1. From there, the RS232 data goes directly to a rear panel DB9 connector.
U8 converts 5-volt logic-level data to +/-12 volt data in RS232C form, and vice-versa. A charge pump
power supply on the chip converts the +5 volt DC power to the +/-12 volt levels required. The charge
pump uses capacitors (C28 to C31) to generate voltages.
NOTE:
The RS232 serial port data transmission rate of the base station is 115.2 KBPS.
Modem Switching
This section displays the connector wiring and modem switching circuitry. Connector J7 is routed to the
front-panel TX, CD, and RX1-RX3 LED indicators. The base station will also accept modulation from an
external source (modem or amplified microphone audio). Transmission gate U10A switches this signal
source.
