SECTION 1: THEORY OF OPERATION
369548.DOC
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Receiver Injection
(refer to schematic on page 20 & 21)
This displays a serial data input/output interface, synthesizer, and VCO. The I/O interface circuitry
accepts clock, serial data, and enable signals from the System Controller Board via terminal block TB1. A
lock detect (LD) status output is returned to the System Controller Board from the synthesizer. U6 is a
hex Schmidt Trigger inverter, which squares up incoming signals for reliable operation of the synthesizer
chip. This is necessary because of a cable run between the two (2) boards.
The main section of this board is synthesizer chip (U5). The device contains the key components of a
phase locked loop (PLL), including a 1.1 GHz prescaler, programmable divider, and phase detector. In
operation, the desired frequency is loaded into U5 as a clocked serial bit stream via the CLK and DATA/I
inputs. The lock detection circuitry consists of inverters U6E/U6F, diode CR1, and resistor R3. When the
synthesizer is in lock, the LD pin on U5 is high, making the LD output on terminal block TB1 high.
The UHF injection signal is generated by module VCO1. This device is a wide-range voltage controlled
oscillator (VCO). A voltage on the C input determines the VCO frequency. The voltage is generated by
the phase detector output (PD/O) of U5, which drives a loop filter consisting of R2, C23, C7, R5, C15, and
C16. The filter integrates the pulses, which normally appear on PD/O into a smooth DC control signal for
the VCO. The output of VCO1 is attenuated by module AT1, resulting in improved VCO stability.
Reference module (Y1) provides a high-stability 10 MHz reference frequency. Y1 is a voltage controlled,
temperature controlled crystal oscillator (VCTCXO). This device also has a VC input which accepts a
control voltage from pot R7. The pot permits a slight shift in the reference frequency which enables the
three (3) receivers to be tuned precisely to the assigned receive frequency. A diode (CR2) provides
additional voltage regulation, improving the frequency stability of reference Y1.
The RF output circuitry consists of RF amplifier (U4), and two-way power splitters (U3, U1, and U2). U4
increases the signal level to correct for losses in the splitters. The splitter U3 provides two (2) RF outputs.
One output drives splitter U1, which provides local oscillator injection for receivers 2 and 3. The other
output drives splitter (U2), which drives receiver 1 and the PLL_FEEDBACK input on chip U5.
Exciter Board
(refer to schematic on page 49)
This section displays the input/output interface, transmitter keying, and power supply circuitry. The
input/output interface is built around terminal block (TB1) and Schmidt Trigger inverters (U4). Incoming
clock, serial data, and chip select signals on block TB1 are squared up by U4. Then they are sent to the
appropriate inputs on the low pass Bessel filter (U2). The EXCDATA source comes from the receive
synthesizer on the Injection Synthesizer Board. A Schmidt Trigger chip is used here because of a cable
ran to the System Controller Board. The synthesizer returns a lock detect output to the Injection
Synthesizer Board via U4D and EXCLD.
A regulator (VR3) powers the T/R switch circuitry. When the System Controller Board makes TXKEY*
low, turning on transistor Q4 and FET Q1. This applies 5-volt power to the TXENABLE output, turning on
the T/R switch on the Power Amplifier Board. At the same time, transistor Q2 conducts, grounding the
KEY* input of the Power Amplifier Board. Finally, inverter U4E goes high and turns on RF switch U5,
connecting the VCO output to the Power Amplifier Board for transmission
.
The power supply consists of two (2) voltage regulators. A regulator (VR1) provides 9-volt power for the
VCO. Another regulator (VR2) provides low noise 5-volt power for the logic circuitry, synthesizer chip,
and analog circuitry.
