REL 1.2
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i.MX6 Qseven PMIC SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Make sure to use suitable level shifter and driver to interface the I2C with the HDMI monitor since i.MX6 CPU’s I2C
cannot operate at the 5 V required by HDMI EDID. In addition, ESD protection must be used on all HDMI single-
ended and differential signals mounted near the HDMI connector. CM2020 from ON semiconductor or similar part
could be considered for ESD protection and I2C level conversion.
For more details, refer Qseven Edge connector pins 131,133,137,139,143,145,149,150,151,152 & 153 on
Note: Customers who develop products using HDMI need to work with DCP (
http://www.digital-cp.com/licensing
) to
get the HDCP license and related device keys.
2.7.11
LPC/GPIO Interface
As per Qseven Specification, If LPC interface is not used on Qseven Edge connector, the same pins can be used for
GPIOs. i.MX6 Qseven PMIC SOM doesn’t support LPC interface instead supports 8 GPIOs on Qseven Edge connector.
i.MX6 CPU GPIO controller provides dedicated general-purpose pins that can be configured as either inputs or
outputs. When configured as an output, it is possible to write to an internal register to control the state driven on
the output pin. When configured as an input, it is possible to detect the state of the input by reading the state of an
internal register. In addition, the GPIO peripheral can produce CORE interrupts.
For more details, refer Qseven Edge connector pins 185 to 192 on
Note: Most of the i.MX6 Pins which are connected to Qseven Edge connector and Expansion connectors can be
configured as GPIO with interrupt capable (if not used as other interface).
2.7.12
SPI Interface
i.MX6 Qseven PMIC SOM supports one SPI interface with two chip selects on Qseven Edge connector. i.MX6 CPU’s
eCSPI2 is used for SPI interface which supports full-duplex synchronous four-wire serial interface with DMA. It
supports 32bit x 64 entry FIFO for both transmit and receive data. It can be configured as Master or Slave. Also
polarity and phase of the Chip Select and SPI Clock are configurable.
For more details, refer Qseven Edge connector pins 199 to 203 on
2.7.13
CAN Interface
i.MX6 Qseven PMIC SOM supports one CAN interface on Qseven Edge connector. i.MX6 CPU’s FLEXCAN1 module is
used for CAN interface which supports CAN protocol according to the CAN 2.0B protocol specification. It supports
programmable bit rate up to 1 Mb/sec with both standard and extended message frames. Also it supports 64
Message Buffers. To connect external CAN module to this bus, it is necessary to add transceiver in between.
For more details, refer Qseven Edge connector pins 129 and 130 on
