REL 1.2
Page 19 of 56
i.MX6 SODIMM SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
2.6.4
SATA Interface
i.MX6 SODIMM SOM supports one SATA II lane on SODIMM Edge connector. i.MX6
CPU’s SATA controller core with
integrated PHY is used for SATA Interface which can support SATA II with transfer rate of 3Gbps and backward
compatible to SATA I with transfer rate of 1.5Gbps.
For more details, refer SODIMM Edge connector pins 82, 84, 85 & 87 on
Note: SATA interface is not supported in i.MX6 Duallite and i.MX6 Solo CPU.
2.6.5
USB2.0 OTG Interface
i.MX6 SODIMM SOM supports one High Speed USB2.0 OTG interfaces on SODIMM Edge connector.
i.MX6 CPU’s
USB2.0 OTG controller core with integrated PHY is used for USB2.0 OTG interface which can operate in High Speed
operation (480 Mbps
), Full Speed operation (12Mbps) and Low Speed operation (1.5 Mbps). i.MX6 CPU’s OTG
controller core can operate in Host mode and Device (Peripheral) mode. Also USB ID input from SODIMM Edge
connector is connected to i.MX6 CPU’s USB_OTG_ID for auto USB hos
t or device detection.
For more details, refer SODIMM Edge connector pins 74, 77, 81 & 83 on
2.6.6
USB2.0 Host Interface
i.MX6 SODIMM SOM supports one USB2.0 Host interface on SODIMM Edge connector.
i.MX6 CPU’s
USB2.0 Host
controller core with integrated PHY is used for USB2.0 Host interface which can operate in High Speed operation
(480 Mbps), Full Speed operation (12Mbps) and Low Speed operation (1.5 Mbps).
For more details, refer SODIMM Edge connector pins 39, 140, 188 & 190 on
2.6.7
SD Interface
I.MX6 SODIMM SOM supports one SDIO interface port on SODIMM Edge connector. i.MX6
CPU’s
uSDHC3 controller
is used for SD interface which is fully compliant with SD Memory Card Specifications v3.0 including high-capacity
SDHC cards up to 32 GB & SDXC cards up to 2TB and SDIO Card Specification Part E1, v1.10. It supports 1-bit or 4-bit
transfer mode for SD and SDIO cards up to UHS-I SDR104 mode (104 MB/s max). i.MX6 SODIMM SOM can also
support SDIO card detect input from SODIMM Edge connector through i.MX6 CPU pin EIM_D25 .
For more details, refer SODIMM Edge connector pins 105, 107, 108, 109, 111, 112 & 114 on
Note: If EIM_D25 is not used for SDIO card detect, the same pins can be used for SS3 chip select
(eCSPI2_SS3(EIM_D25) of eCSPI2 interface.
Note: If more SDIO interfaces are required on SODIMM edge, it can be supported by modifying the CPU IOMUX
setting on SODIMM edge pins. Contact iWave for more details.