REL1.1
Page 39 of 51
iWave Systems Technologies Pvt. Ltd.
RZ/G1C SBC Hardware User Guide
Table 9: Expansion Connector3 Pin Assignment
Pin
No.
Signal Name
CPU Ball Name/
Pin Number
Signal Type/
Termination
Description
1
VI0_CLK/AVB_COL(GP5_18
)
SSI_SCK1_A/
H2
I, 3.3V CMOS
Video Input Channel0 pixel clock.
Note: This signal is optionally connected
to Ethernet PHY Collision pin through
resistor and default not populated.
2
VI0_HSYNC(GP5_30)
AUDIO_CLKC_A/
E4
I, 3.3V CMOS
Video
Input
Channel0
Horizontal
synchronization signal.
3
VI0_VSYNC(GP5_31)
AUDIO_CLKOUT
_A/E1
I, 3.3V CMOS
Video
Input
Channel0
Vertical
synchronization signal.
4
VI0_CLKENB(GP5_28)
AUDIO_CLKA_A/
E2
I, 3.3V CMOS
Video Input Channel0 data enable signal.
5
GND
GND
Power
Ground.
6
VCC
VCC_5V
O, 5V Power
5V Power Supply.
7
PWM2_D(GP5_27)
SSI_SDATA9_A/
K1
O, 3.3V CMOS
Pulse Width Modulated output 2.
8
VI0_G2(GP4_4)
MSIOF0_RXD_A
/A6
I, 3.3V CMOS
Video Input0 Data 2.
9
VI0_G4(GP4_6)
MSIOF0_SCK_A/
A5
I, 3.3V CMOS
Video Input0 Data 4.
10
VI0_G3(GP4_5)
MSIOF0_TXD_A/
B6
I, 3.3V CMOS
Video Input0 Data 3.
11
VI0_G7(GP5_10)
SSI_WS0129_A/
G1
I, 3.3V CMOS
Video Input0 Data 7.
12
VI0_G0(GP4_2)
SCL1_A/
C5
I, 3.3V CMOS
Video Input0 Data 0.
13
VI0_G1(GP4_3)
SDA1_A/
D5
I, 3.3V CMOS
Video Input0 Data 1.
14
VI0_G5(GP5_8)
SSI_SDATA7_A/
F5
I, 3.3V CMOS
Video Input0 Data 5.
15
GND
GND
Power
Ground.
16
VI0_G6(GP5_9)
SSI_SCK0129_A/
G2
I, 3.3V CMOS
Video Input0 Data 6.
17
SCIF1_RX1_B(GP5_19)
SSI_SDATA8_A/
F4
I, 3.3V CMOS
SCIF1 Serial data receiver input for
debug.
18
SCIF4_RX4_B(GP1_2)
D2/
AC2
I, 3.3V CMOS
SCIF4 Serial data receiver input.
19
SCIF1_TX1_B(GP5_20)
SSI_WS1_A/
H1
O, 3.3V CMOS
SCIF1 Serial data transmitter output for
debug.
20
SCIF4_TX4_B(GP1_3)
D3/
AC1
O, 3.3V CMOS
SCIF4 Serial data transmitter output.