REL1.1
Page 41 of 51
RZ/G1C SBC Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Interface/
Function
Expansion
Connnector1
Pin Numbers
RZ/G1C CPU
Pin Number
Function 1
Function 2
Function 3
Function 4
Function 5
Function 6
Function 7
Function 8
GPIO
Default
State
GPIOs
11
C6
MSIOF0_SS1
_A
Reserved
DU1_DR6
Reserved
QSPI1_IO3
SSI_SDATA8_
B
GP4_8
GP4_8
13
G4
SSI_SCK4_A
AVB_MAGIC
VI0_R4
GP5_15
GP5_15
15
J4
SSI_SDATA1_
A
HRX1_B
VI0_DATA1_
VI0_B1
GP5_21
GP5_21
31
B5
MSIOF0_SYN
C_A
PWM1_A
Reserved
DU1_DR5
Reserved
QSPI1_IO2
SSI_SDATA7_
B
GP4_7
GP4_7
33
E3
AUDIO_CLKB
_A
SDA0_B
Reserved
TANS2
VI0_FIELD
GP5_29
GP5_29
35
C4
SDA2_A
MSIOF1_SYN
C_B
DU1_DB7
AUDIO_CLKO
UT_C
GP4_25
GP4_25
37
B4
SCL2_A
MSIOF1_SCK
_B
DU1_DB6
AUDIO_CLKC
_C
SSI_SCK4_B
GP4_24
GP4_24
12
D6
MSIOF0_SS2
_A
Reserved
DU1_DR7
Reserved
QSPI1_SSL
GP4_9
GP4_9
16
AB11
DU0_DOTCL
KOUT1
Reserved
MSIOF2_RXD
_B
CS1#/A26
GP2_26
GP2_26
18
AE3
EX_WAIT0
CAN_CLK_B
SCIF_CLK_A
GP1_22
GP1_22
22
J1
SSI_SDATA2_
A
HRTS1#_B
VI0_DATA4_
VI0_B4
GP5_24
GP5_24
32
Y1
D15
MSIOF2_SS2
PWM4_A
CAN1_TX_B
IRQ2
AVB_AVTP_
MATCH_A
GP1_15
GP1_15
36
Y22
USB0_PWEN
GP0_0
GP0_0
38
AC5
QSPI0_IO3
RD#
GP1_20
GP1_20
40
A3
SSI_SCK5_A
DU1_DOTCL
KOUT1
GP5_0
GP5_0
29
AB3
D4
IRQ3
TCLK1_A
PWM6_C
Reserved
GP1_4
GP1_4
7
AE2
CLKOUT
GP0_4
GP0_4