REL1.1
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iWave Systems Technologies Pvt. Ltd.
RZ/G1C SBC Hardware User Guide
2.5
Memory
2.5.1
DDR3 SDRAM
The RZ/G1C SBC supports 512MB DDR3 RAM memory by default. This is connected to CPU
’s DBSC3 DDR3 controller
in 32bit x 1ch mode where it uses two 256MB DDR3-SDRAM ICs. This device operates at 1.5V voltage level. DDR3-
SDRAM ICs are physically located on top side of the SBC. The RAM size can be expandable up to maximum of 2GB.
2.5.2
SPI NOR Flash
The RZ/G1C SBC supports 16MB SPI NOR Flash as default boot device. This is connected to QSPI controller of the
RZ/G1C CPU and operates at 3.3 Voltage level. While RZ/G1C booting, boot program in the on-chip ROM starts up
the QSPI and SYS-DMAC channel 1, and transfers the loader program previously stored in the SPI Flash to the on-chip
RAM via the QSPI controller. After loader program is transferred, the program automatically jumps to the top
address of the loader program. The SPI flash memory is physically located on bottom side of the SBC.
To program the boot code in to the SPI flash (for the first time or if boot code is corrupted), use
iWave’s
RZ/G1C SPI
Programmer Board through SPI Flash Programming Header (J6) (or) JTAG debugger through JTAG Header (J14).
Optionally the external SPI programmer can be used for programming the SPI flash through SPI Flash Programming
Header (J6).
2.5.3
eMMC Flash
The RZ/G1C SBC supports 8GB eMMC Flash memory as mass storage. eMMC is directly connected to the MMC0
controller of the RZ/G1C CPU. It supports MMC 4.4.1 base, HS200 transfer modes upto 156 MHz and operating at
1.8V Voltage level. The eMMC flash memory is physically located on top side of the SBC. The memory size of the
eMMC Flash can be expandable.
