REL0.1
Page 37 of 95
Kintex Ult FPGA SOM Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
B2B-1
Pin No
B2B Connector1
Signal Name
FPGA Pin
Name
FPGA
Bank
FPGA Pin
No
Signal Type/
Termination*
Description
14
PL_AM22_LVDS
92_L11N
IO_L11N_AD1
N_92
92
AM22
IO, 3.3V
Bank92 IO11 differential negative.
Same pin can be configured as
PLSYSMON
differential
analog
input1 negative or Single ended I/O.
16
PL_AU22_LVDS9
2_L3P
IO_L3P_AD9P_
92
92
AU22
IO, 3.3V
Bank92 IO3 differential positive.
Same pin can be configured as
PLSYSMON
differential
analog
input9 positive or Single ended I/O.
50
PL_AV22_LVDS9
2_L3N
IO_L3N_AD9N_
92
92
AV22
IO, 3.3V
Bank92 IO3 differential negative.
Same pin can be configured as
PLSYSMON
differential
analog
input9 negative or Single ended I/O.
22
PL_AP23_LVDS9
2_L8N_HDGC
IO_L8N_HDGC
_AD4N_92
92
AP23
IO, 3.3V
Bank92 IO8 differential negative.
Same pin can be configured as HDGC
Global Clock Input differential
negative or PLSYSMON differential
analog input4 negative or Single
ended I/O.
24
PL_AN23_LVDS9
2_L8P_HDGC
IO_L8P_HDGC_
AD4P_92
92
AN23
IO, 3.3V
Bank92 IO8 differential positive.
Same pin can be configured as HDGC
Global Clock Input differential
negative or PLSYSMON differential
analog input4 positive or Single
ended I/O.
40
PL_AP24_LVDS9
2_L9N
IO_L9N_AD3N_
92
92
AP24
IO, 3.3V
Bank92 IO9 differential negative.
Same pin can be configured as
PLSYSMON
differential
analog
input3 negative or Single ended I/O.
44
PL_AN24_LVDS9
2_L9P
IO_L9P_AD3P_
92
92
AN24
IO, 3.3V
Bank92 IO9 differential positive.
Same pin can be configured as
PLSYSMON
differential
analog
input3 positive or Single ended I/O.
46
PL_AR22_LVDS9
2_L4P
IO_L4P_AD8P_
92
92
AR22
IO, 3.3V
Bank92 IO4 differential positive.
Same pin can be configured as
PLSYSMON
differential
analog
input8 positive or Single ended I/O.
48
PL_AT22_LVDS9
2_L4N
IO_L4N_AD8N_
92
92
AT22
IO, 3.3V
Bank92 IO4 differential negative.
Same pin can be configured as
PLSYSMON
differential
analog
input8 negative or Single ended I/O.