Rev 2.0
Page 23 of 164
Generic Qseven Carrier Board Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
115
eDP0_TX3-/
LVDS_A3-
Input
LVDS
LVDS primary channel differential pair3
negative.
116
eDP1_TX3-/
LVDS_B3-
Input
LVDS
LVDS secondary channel differential
pair3 negative.
117
GND15
Power
0V
Ground.
118
GND16
Power
0V
Ground.
119
e/
LVD
Input
LVDS
LVDS primary channel differential clock
positive.
120
e/
LVD
Input
LVDS
LVDS secondary channel differential
clock positive.
121
eDP0_AUX-/
LVDS_A_CLK-
Input
LVDS
LVDS primary channel differential clock
negative.
122
eDP1_AUX-/
LVDS_B_CLK-
Input
LVDS
LVDS secondary channel differential
clock negative.
123
LVDS_BLT_CTRL/
GP_PWM_OUT0
Input
3.3V CMOS
LVDS LCD Panel backlight brightness
control.
124
GP_1-Wire_Bus
Input/Output
3.3V CMOS
HDMI CEC bus.
125
GP2_I2C_DAT/
LVDS_DID_DAT
Input/Output
3.3V CMOS/
4.7K Pull-up
Display ID DDC data line used for LVDS
flat panel detection.
126
eDP0_HPD#/
LVDS_BLC_DAT
Input/Output
3.3V CMOS/
4.7K Pull-up
Control data signal for external SSC
clock chip.
127
GP2_I2C_CLK/
LVDS_DID_CLK
Input
3.3V CMOS/
4.7K Pull-up
Display ID DDC clock line used for LVDS
flat panel detection.
128
eDP1_HPD#/
LVDS_BLC_CLK
Input
3.3V CMOS/
4.7K Pull-up
Control clock signal for external SSC
clock chip.
129
CAN0_TX
Input
3.3V CMOS
CAN channel one TX line.
130
CAN0_RX
Output
3.3V CMOS
CAN channel one RX line
131
D/
T
Input
TMDS
HDMI differential clock positive.
132
RSVD2
(Differential Pair)
NC
NC
Default NC.
Connected to 2
nd
Pin of SDVO Header
(J47) through resistor and default not
populated.
133
DP_LANE3-/
TMDS_CLK-
Input
TMDS
HDMI differential clock negative
