ADwin-Pro II
Hardware, manual Dec. 2018
47
Pro II: Multi-IO-Module
Pro II-MIO-D12 Rev. E
ADwin
Please note, that the pins of the counter inputs have double functionality. It is
technically permissable, to use both functions (timer and other functions) at the
same time, though it may not be useful.
Up/down counter
The up/down counter of a block can be operated in 2 modes:
– Clock / direction (CLK and DIR signals)
A negative edge at the
CLK
input is the counting impulse for the 32-bit
counter. The
DIR
signal sets the counting direction, TTL high means a
count-up, TTL low means a count-down.
Via software, you can invert the signals at the inputs
CLK
and
DIR
(see
P2_Cnt_Mode
) and thus change the triggering edge as well as the
count direction.
You can latch the counter values program-controlled or you can influ-
ence the counter by an external
CLR/LATCH
signal.
Depending on the programming the CLR/LATCH signal has either the
effect that the counter values are cleared (CLR) or that the counter val-
ues are latched (LATCH). This function will only be effective when it is
released by
P2_Cnt_Clear_Enable
or
P2_Cnt_Latch_Enable
.
The counter is cleared or latched with a rising adge at input
CLR/LATCH
.
During the latch process the frequency of the measurement can be de-
termined by getting the difference of two read latch values, because this
difference defines the number of pulses between the two reading pro-
cesses.
– Four edge evaluation (A and B signals)
The four edge evaluation changes the signals (which should be 90° pha-
se-shifted) of a connected incremental encoder at the inputs A and B to
CLK and DIR signals. For this you have to program the inputs corre-
spondingly (see "
ADwin-Pro
System Description, Programming in
AD-
basic
").
Since every edge of the A and B signals generates a count impulse, the
resolution is increased by factor 4. If the encoder has a reference signal,
it can be used to clear or latch the counter (after release of the CLR or
LATCH input). The counter is cleared when the signalsA, B and CLR are
on logic "1" (software-selectable: clear, when only the CLR signal is on
logic "1").
PWM Counter
The PWM counter of the counter block analyzes the signals at the PWM inputs.
With
P2_Cnt_Mode
, you set the input pin (
A/CLK
,
B/DIR
or
CLR/LATCH
) and
the triggering edge.
Via software instructions the following data can be read directly:
– frequency and duty cycle (with
P2_Cnt_Get_PW
)
– high and low time (with
P2_Cnt_Get_PW_HL
)
The counter inputs are provided on the 25-pole D-Sub connector
Conn2
; pin
assignment see fig. 30.
If PWM counters are evaluated with standard instructions, no further knowl-
edge is required.
If you require other evaluation methods, you can use several registers
assigned to each PWM counter to create a solution. You find a description of
PWM registers on page 140 (module Pro II-CNT-x Rev. E). Use the evaluation
with PWM registers for special solutions only.
