CV-M9 GE
- 44 -
0xA848
Seq. ROI size-Y 7
R/
W
4
ROI1 size y-7
0xA84C
Seq. ROI size-Y 8
R/
W
4
ROI1 size y-8
0xA850
Seq. ROI size-Y 9
R/
W
4
ROI1 size y-9
0xA854
Seq. ROI size-Y 10
R/
W
4
ROI1 size y-10
0xA858
Seq. ROI offset-X 1
R/
W
4
ROI1 offset x-1
0xA85C
Seq. ROI offset-X 2
R/
W
4
ROI1 offset x-2
0xA860
Seq. ROI offset-X 3
R/
W
4
ROI1 offset x-3
0xA864
Seq. ROI offset-X 4
R/
W
4
ROI1 offset x-4
0xA868
Seq. ROI offset-X 5
R/
W
4
ROI1 offset x-5
0xA86C
Seq. ROI offset-X 6
R/
W
4
ROI1 offset x-6
0xA870
Seq. ROI offset-X 7
R/
W
4
ROI1 offset x-7
0xA874
Seq. ROI offset-X 8
R/
W
4
ROI1 offset x-8
0xA878
Seq. ROI offset-X 9
R/
W
4
ROI1 offset x-9
0xA87C
Seq. ROI offset-X 10
R/
W
4
ROI1 offset x-10
0
0xA880
Seq. ROI offset-Y 1
R/
W
4
ROI1 offset y-1
0xA884
Seq. ROI offset-Y 2
R/
W
4
ROI1 offset y-2
0xA888
Seq. ROI offset-Y 3
R/
W
4
ROI1 offset y-3
0xA88C
Seq. ROI offset-Y 4
R/
W
4
ROI1 offset y-4
0xA890
Seq. ROI offset-Y 5
R/
W
4
ROI1 offset y-5
0xA894
Seq. ROI offset-Y 6
R/
W
4
ROI1 offset y-6
0xA898
Seq. ROI offset-Y 7
R/
W
4
ROI1 offset y-7
0xA89C
Seq. ROI offset-Y 8
R/
W
4
ROI1 offset y-8
0xA8A0
Seq. ROI offset-Y 9
R/
W
4
ROI1 offset y-9
0xA8A4
Seq. ROI offset-Y 10
R/
W
4
ROI1 offset y-10
0
GPIO Registers:
0xA8B0 xTTL_LVDS
Select
R/
W
4
0x00
0x01
TTL In 1, TTL IN active
LVDS IN active
0
0xB000
Counter Clock source
R/
W
4
0x00
0x01
25MHz
Pixel Clock
0
0xB004
Counter Divide by
Value
R/
W
4
0x000
0x001
0x002
|
0xFFF
Bypass
Divide by 2
Divide by 3
|
Divide by 4096
0
0xB008
Length Counter 0
R/
W
4
0x00001 to 0xFFFFF
Defines the length of the
counter
1
0xB00C
Start pt. Counter 0
R/
W
4
0x00001 to 0xFFFFF Defines the starting point of the
counter
0