SDRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of CAS latency
depends on the DRAM timing. The settings are: 2 and 3.
SDRAM Cycle Time Tras/Trc
Select the number of SCLKs for an access cycle. The settings are: 5/7 and 6/8.
SDRAM RAS-to-CAS Delay
This field let’s you insert a timing delay between the CAS and RAS strobe signals,
used when DRAM is written to, read from, or refreshed.
Fast
gives faster
performance; and
Slow
gives more stable performance. This field applies only when
synchronous DRAM is installed in the system. The settings are: 2 and 3.
SDRAM RAS Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge
before DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain
date.
Fast
gives faster performance; and
Slow
gives more stable performance. This
field applies only when synchronous DRAM is installed in the system. The settings
are: 2 and 3.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh,
resulting in better system performance. However, if any program writes to this
memory area, a system error may result. The settings are: Enabled and Disabled.
Video BIOS Cacheable
Select Enabled allows caching of the video BIOS, resulting in better system
performance. However, if any program writes to this memory area, a system error may
result. The settings are: Enabled and Disabled.
Memory Hole At 15M-16M
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved, it cannot be cached. The user information of peripherals that need to use this
area of system memory usually discusses their memory requirements. The settings are:
Enabled and Disabled.
CPU Latency Timer
During Enabled, A deferrable CPU cycle will only be Deferred after it has been in a
Snoop Stall for 31 clocks and another ADS# has arrived. During Disabled, A
deferrable CPU cycle will be deferred immediately after the GMCH receives another
ADS#.
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions
cycles. Select Enabled to support compliance with PCI specification version 2.1. The
settings are: Enabled and Disabled.
On-Chip Video Window Size
This option enabled/disabled the on-chip video windows size for VGA driver use. The
settings are: enabled, Disabled.
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