MX-G71R
1-39
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
XIN
Vssd
Vddd
MODE
RST
RDDA
RDCL
RDS-ID/READY
XOUT
TBS
CIN
FLOUT
Vssa
Vdda
MPXIN
VREF
1. Pin Assignment
2.Block diagram
Top View
LC72723 (IC3) : RDS demodulation
Vdda
Vssa
MPXIN
TEST
VREF
FLOUT
CIN
Vddd
Vssd
RDDA
RDCL
MDDE
RST
RDS-ID/
READY
XDUT
XIN
REFERENCE
VOLTAGE
ANTIALIASING
FILTER
57kHz
BPF
(SCF)
VREF
SMOOTHING
FILTER
PLL
(57kHz)
CLOCK
RECOVERY
(1187.5kHz)
DATA
DECODER
RAM
(128-bits)
RDS-ID
DETECT
CLK(4.332MHz)
OSC
TEST
3. Pin functions
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
No.
Symbol
Function
VREF
MPXIN
Vdda
Vssa
FLOUT
CIN
TEST
XOUT
XIN
Vssd
Vddd
MODE
RST
RDDA
RDCL
RDS-ID
READY
I/O
O
O
O
O
O
I
I
I
I
I
I
I/O
Reference voltage output (Vdda/2)
Baseband (multiplexed) signal input
Analog power supply (+5V)
Analog ground
Subcarrier input (comparator input)
Sub carrier input (filter output)
Test input
Crystal oscillator input (external reference input)
Crystal oscillator output (4.332MHz)
Digital ground
Digital power supply
Read mode setting (0:master,1:slave)
RDS-ID/RAM reset (positive polarity)
RDS data output
RDS clock output (master mode)/RDS clock input (slave mode)
RDS-ID/READY output (negative polarity)
Vdda
Vssa
MPXIN
TEST
VREF
FLOUT
CIN
Vddd
Vssd
RDDA
RDCL
MDDE
RST
RDS-ID/
READY
XDUT
XIN
REFERENCE
VOLTAGE
ANTIALIASING
FILTER
57kHz
BPF
(SCF)
VREF
SMOOTHING
FILTER
PLL
(57kHz)
CLOCK
RECOVERY
(1187.5kHz)
DATA
DECODER
RAM
(128-bits)
RDS-ID
DETECT
CLK(4.332MHz)
OSC
TEST
Summary of Contents for CA-MXG71R
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Page 61: ...MX G71R 3 2 M E M O ...