(No.YF219)2-19
2-20(No.YF219)
yf219_y10718001a_rev0.1
MAIN(OP DRV)
1
0
IC4901
AN41904A-X
Dch
Cch
Ach
Bch
REG_4.65V
CLK27O
M_REG4.65_L4903
REG_2.8V_L4901
REG_4.65V_L4902
REG_2.8V
C4902
C4934
OPEN
C4914 220p
C4905
0.1
C4912
0.1
C4923
OPEN
C4927
OPEN
C4916
0.1
C4907
0.1
C4904
C4922 0.1
C4924
OPEN
C4908
0.1
C4933
OPEN
C4940
OPEN
C4926
OPEN
C4925
OPEN
C4937
OPEN
C4909
0.01
C4936
OPEN
C4901
0.1
C4941
O.1
C4913
0.1
C4910
OPEN
C4942
0.1
T
C4903
10/6.3
T
C4935
10/6.3
T
C4932
10/10
C4921
(1005)
CH
C4915
120p
CH
C4911
100p
IC4903
R1100D311C-X
OPEN
1
Vout
2
VDD
3
GND
IC4902
MM1614GN-X
OPEN
1
Cont
2
GND
3
Noise
4
Vout
5
Vin
IC4904
BA10358FVM-W
8
VCC
7
OUT2
6
-IN2
5
+IN2
4
VEE
3
+IN1
2
-IN1
1
OUT1
1 N.C.
27 NT
23 GNDD
52 DVDD
21 RETB
56 SCK
2 PLS3
37 PLS4
20 MONI0
29 TEST
24 CS
25 SIN
22 OSCIN
53 VD_IS
55 SOUT
58 PDWNB
54 VD_FZ
57 PLS1
30 PLS2
26 MODESEL
10
N.C.
17
A1
50
MVCCA
16
MGNDA
49
A2
15
B2
48
B1
47
MVCCB
14
C1
13
MGNDB
46
C2
12
D2
44
MVCCC
45
D1
19
N.C.
42
8
6
AVDD5
39
GND5A
40
5
7
41
11
DMP0
18
DMP1
3
AVDD3
31
GNDA
4
IRISOUTA
51
MONI1
36
TEST2
38
RHTRIN
33
28
N.C.
62
34
60
VREF
61
32
59
CREFIN
63
REF
35
SENS
64
GAININ
43
LED1
9
LED2
L4904
NQL38DK-100X
L4902
NQLC32M-100X
L4901
NQR0602-001X
L4903
NQL38DK-100X
10u
Q4901
RPM-22PB
R4955
33k
R4905
R4909
1M
R4916
10k
R4960
OPEN
R4901
2K
R4920
6.8k
R4903
8.2k
R4910
R4961
OPEN
R4919
10K
R4953
R4927
OPEN
R4902
10K
R4951
10K
R4962
R4906
560k
R4908
OPEN
R4925
OPEN
R4950
150K
R4931
150
R4963
OPEN
R4954
R4904
10k
R4917 470k
R4907
1M
R4949
10K
R4912
10K
R4911
100
R4924
120k
H_GAIN
H_OFFSET
VDMDA
M_REG4.65
OPOSD_RST
CLK27O
GND
OPDRV_VD
TO PARAGON3
GND
REG_4.65V
HGOUT-
OPOSD_OUT
VD_FZ
OPOSD_CLK
OPDRV_PS
OPDRV_CS
REG_2.8V
DUMP-
Z_LED
DUMP+
HGOUT+
DRIVE-
GND
FOCUS01
ZOOM03
F_VCC
OPOSD_IN
DRIVE+
FOCUS04
HGVCC+
FOCUS02
FOCUS03
ZOOM04
TO MAIN IF(CN4901)
HGVSS-
ZOOM01
ZOOM02
TL4912
TL4917
TL4911
TL4915
TL4916
TL4913
TL4914
(N4)
(N1)
(W3)
(W4)
(N3)
(W1)
(W2)
(N2)
10u
10
µ
0.022
µ
10u
10K
0
Ω
470
120
10K
TO CPU
MAIN(OP DRV) SCHEMATIC DIAGRAM
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.