JVC GR-DA30UC, Schematic Diagrams

(No.YF219) 2-9

2-10(No.YF219)

yf219_y20445001a_rev0.1

MAIN(MDA)

1

0

C1624

0.01

C1627

0.0047

C1626

0.0047

C1628

0.22

C1606
0.0015

C1605
0.1

C1701

OPEN

C1625

100p

C1702

0.1

C1632
0.47

C1614

(2125)

C1631

(2125)

C1633
0.47

C1634

OPEN

C1635

OPEN

C1636

OPEN

C1607
0.047

C1622

0.022

C1623

0.047

C1629
0.22

C1615

OPEN

C1617

OPEN

C1630

0.22

C1601
0.01

C1618

0.0022

C1602

(2125)

C1637
1

C1621
1

C1619

0.0022

C1616

OPEN

C1620

0.0022

T

C1603
10

Ǵ

/6.3

D1604
OPEN

D1603

DAP222-X

D1602

OPEN

F1602
NMFZ024-R50X-A

F1601

NMFZ024-R25X-A

IC1701

BA10358FVM-W

8

7

6

5

4

3

2

1

IC1702

BA2903FVM-W

8

7

6

5

4

3

2

1

IC1601

BD6637KV

1

NC

2

C.U

3

C.V

4

C.RNF

5

C.W

6

NC

7

NC

8

C.HU+

9

C.HU-

10

C.HV+

11

C.HV-

12

C.HW+

13

C.HW-

14

D.PGSMT

15

D.PGAMP

16

D.PGIN-

17

D.PFGIN+

18

D.FGIN-

19

D.FGAMP

20

D.FGSMT

21

VCC

22

D.DETECT

23

D.ISET

24

D.SL1

25

D.SL2

26

UNREG

27

NC

28

D.VM

29

D.VS

30

D.EC

31

D.PCI

32

D.PCV

33

D.COM

34

D.U

35

D.V

36

D.RNF

37

D.W

38

NC

39

L.FRB

40

L.REF

41

L.FWD

42

NC

43

L.GND

44

L.REV

45

L.VM

46

C.FGIN+

47

C.FGIN-

48

C.FGAMP

49

C.FGSMT

50

NC

51

VG

52

CP1

53

CP2

54

NC

55

GND

56

GDX

57

PS

58

C.RCC

59

C.FRB

60

C.VM

61

C.VS

62

C.EC

63

C.PCI

64

C.PCV

L1602
NQLC32M-100X

10

L1601
NQLC32M-100X

10

Q1601

SUR551H-W

4

6

1

2

3

R1616

3.9K

R1620
68K

R1621

10K

R1629
560K

R1622
10K

R1625

680

R1612
68K

R1711
1K

R1635

2.7K

R1636

12K

R1637
150k

R1632

OPEN

R1703
2.2K

R1702
2.2K

R1701
82K

R1710
120K

R1709
10K

R1705
2.2K

R1704
2.2K

R1604
100K

R1708
120K

R1633

OPEN

R1634

OPEN

R1611
270

R1610
270

R1706
82K

R1601
680

R1624

18K

R1712
1K

R1617
0.33

R1603
4.7K

R1602
120K

R1613
1K

R1614

0.33

R1707
10K

D_PFG+

M_REG4.65

REG_2.8V

M_UNREG

S_RL+

S_RL-

T_RL+

T_RL-

CAP_PWR

L_FRB

GND

LD_ON

DRUM_PWR

CAP_REF

C_FRB

GND

HG_U+

HG_U-

HG_V+

HG_V-

DRUM_REF

GND

D_FG-

D_PG-

HG_W+

COIL_COM

D_COIL_U

D_COIL_V

D_COIL_W

C_FG+

C_FG-

C_COIL_U

C_COIL_V

C_COIL_W

HG_W-

MDA_PS

DRUM_FG

DRUM_PG

LOAD_REV

LOAD_FWD

S_REEL

T_REEL

DRUM_ERR

CAP_ERR

HG_BS+

CAP_FG

TO CPU

MECHA_VCC

HG_BS-

10

µ

10

µ

10

µ

*

*

*

R20

R50

TO MAIN IF

(CN1601)

TO MAIN IF

(CN1602)

TO REG

TO MAIN IF
(CN1603)

TO CPU

TO MAIN IF(CN1604)

!

!

MAIN(MDA) SCHEMATIC DIAGRAM

NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
 

2. The parts with marked (  ) is not used.