2-19(No.YF146)
MCLKI
TG_HD
MCLKI
TG_HD
FLDCPU
TG_VD
TG_VD
HDIRS
VDIRS
R4413
1k
C4402
0.1
GND
REG_3.1V
MCLKI
R4414
1k
L4401
NQR0129-002X
TG_VD
TG_HD
C4401
4.7
AFE_RST
R4402 100
IC4401
JCY0228
1
CLR
2
NC
3
NC
4
NC
5
FLDCPU
6
GND
7
NC
30
VDD
31
NC
32
SMC
33
TDI(SIN)
34
TDD(SOUT)
35
TMS
36
TCK
37 TRST
38 NC
39 NC
40 NC
41 VDTG
42 NC
43 NC
44 HDTG
45 NC
46 NC
47 NC
48 MCLKI
C4403 0.1
R4401 0
MAIN(GA)
1
0
TO OP DRV
TO MAIN IF(CN105),
P.PRCS
TO SUB CPU,P.PRCS
MAIN(GA) SCHEMATIC DIAGRAM
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.