RX-7001PGD
1-17
1. Pin layout
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
XT
FM/AM
CE
DI
CLOCK
DO
FM/ST/VCO
AM/FM
SDIN
XT
GND
LPFOUT
LPFIN
PD
VCC
FMIN
AMIN
IFCONT
IFIN
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
Pin
No.
12
13
14
15
16
17
18
19
20
21
22
Symbol
XT
FM/AM
CE
DI
CLOCK
DO
FM/ST/VCO
AM/FM
LW
MW
SDIN
Symbol
IFIN
IFCONT
AMIN
FMIN
VCC
PD
LPFIN
LPFOUT
GND
XT
Function
X'tal oscillator connect (75kHz)
LOW:FM mode
When data output/input for 4pin(input) and
6pin(output): H
Input for receive the serial data from
controller
Sync signal input use
Data output for Controller
Output port
"Low": MW mode
Open state after the power on reset
Input/output port
Input/output port
Data input/output
Function
IF counter signal input
IF signal output
Not use
AM Local OSC signal output
FM Local OSC signal input
Power suplly(VDD=4.5-5.5V)
When power ON:Reset circuit move
PLL charge pump output(H: Local OSC
frequency Height than Reference frequency.
L: Low Agreement: Height impedance)
Input for active lowpassfilter of PLL
Output for active lowpassfilter of PLL
Connected to GND
X'tal oscillator(75KHz)
I/O
I
O
I
I
I
O
O
O
I/O
I/O
I/O
I/O
I
O
-
I
I
-
O
I
O
-
I
Reference
Driver
Phase
Detector
Charge Pump
Unlock
Detector
Universal
Counter
Swallow Counter
1/16,1/17 4bit
12bit
Programmable
DriverS
Swallow Counter
1/16,1/17 4bit
Data Shift Register & Latch
Power
on
Reset
C
2
B
I/F
1/2
7
8
2
11
13
21
17
6
5
4
3
15
16
22
1
18
19
20
12
2. Block diagram
3. Pin function
LC72136N (IC121) : PLL Frequency synthesizer
Summary of Contents for RX-7001PGD
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