RX-E100SL
1-10
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44
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34
SDOS
I2C
SMUTE
BICK
LRCK
SDTI1
SDTI2
SDTI3
SDTO
DAUX
DFS
DZF2/OVF
RIN+
RIN-
LIN+
LIN-
ROUT1
LOUT1
ROUT2
LOUT2
ROUT3
LOUT3
NC
DZFE
TVDD
D
VDD
D
VSS
PDN
TST
NC
ADIF
CAD1
CAD0
LOOP1
LOOP0/SD
A/CDTI
DIF1/SCL/CCLK
DIF0/CSN
P/S
MCLK
DZF1
A
VSS
A
VDD
VREFH
VCOM
1.Pin layout
AK4527B (IC601) : A/D,D/A Converter
Description of major ICs
AK4527BVQ
Top View
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Pin name
SDOS
I2C
SMUTE
BICK
LRCK
SDTI1
SDTI2
SDTI3
SDTO
DAUX
DFS
NC
DZEF
TVDD
DVDD
DVSS
PDN
TST
SDTO Source Select Pin (Note 1)
"L" : Internal ADC output, "H" : DAUX input
Control Mode Select Pin
"L" : 3-wire Serial, "H" : I
2
C Bus
Soft Mute Pin (Note 1)
When this pin goes to "H", soft mute cycle is initialized.
When returning to "L", the output mute releases.
Audio Serial Data Clock Pin
Input Channel Clock Pin
DAC1 Audio Serial Data Input Pin
DAC2 Audio Serial Data Input Pin
DAC3 Audio Serial Data Input Pin
Audio Serial Data Output Pin
Sub Audio Serial Data Input Pin
Double Speed Sampling Mode Pin (Note 1)
"L" : Normal Speed, "H" : Double Speed
No Connect
No internal bonding.
Zero Input Detect Enable Pin
"L" : mode 7 (disable) at parallel mode,
zero detect mode is selectable by DZFM2-0 bits at serial mode.
"H" : mode 0 (DZF is AND of all six channels)
Output Buffer Power supply Pin, 2.7V~5.5V
Digital Power Supply Pin, 4.5V~5.5V
De-emphasis Pin, 0V
Power-Down & Reset Pin
When "L", the AK4527B is powered-down and the control registers are reset to default
state. If the state of P/S or CAD0-1 changes, then the AK4527B must be reset by PDN.
Test Pin
This pin should be connected to DVSS.
Function
AK4527(1/2)
I/O
I
I
I
I
I/O
I
I
I
O
I
I
-
I
-
-
-
I
I
2. Pin function (1/2)
Summary of Contents for RX-E100SL
Page 31: ...RX E100SL 3 2 M E M O ...
