TH-V70
1-48
K4S643232E-TC60 (IC505) : 512K x 32 bit x 4 banks synchronous DRAM
1. Terminal layout
3. Pin function
VDD
DQ0 - DQ31
VDDQ
VSSQ
N.C
DQM0 - DQM3
WE
CAS
RAS
CS
BA0,BA1
A10,A0 - A2,
A3 - A9
VSS
CKE
CLK
Power for the input buffers and core logic.
Data inputs/outputs are multiplexed on the same pins.
Isolated power supply for the output buffers to provide improved
noise immunity.
Isolated ground for the output buffers to provide improved noise immunity.
This pin is recommended to be left no connection on the device.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Latches column addresses on the positive going edge of the CLK
with CAS low. Enables column access.
Latches row addresses on the positive going edge of the CLK
with RAS low. Enables row access & precharge.
Disables or enables device operation by masking or enabling all
inputs except CLK, CKE and DQM.
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Row/column addresses are multiplexed on the same pins.
Row address : RA
0
- RA
10
, Column address : CA
0
- CA
7
Ground for the input buffers and core logic.
Masks system clock to freeze operation from the next cycle.
CKE should be enabled at least one cycle prior to new command.
Disables input buffers for power down mode.
Active on the positive going edge to sample all inputs.
1,15,29,43
2,4,5,7,8,10,11,
13,74,76,77,79,
80,82,83,85,31,
33,34,36,37,39,
40,42,45,47,48,
50,51,53,54,56
3,9,35,41,49
55,75,81
6,12,32,38,46
52,78,84
14,21,30,57,
69,70,73
16,71,28,59
17
18
19
20
22,23
24,25 - 27,
60 - 66
44,58,72,86
67
68
Pin No.
Symbol
Function
2. Block diagram
CLK
ADD
LCKE
Address Register
LRAS LCBR LWE
CLK
CKE
CS
RAS
CAS
Timing Register
LCAS
Col. Buffer
LCBR
LRAS
WE
DQM
Column Decoder
Latency & Burst Length
Programming Register
LWCBR
LDQM
Output Buffer
Sense AMP
DQi
LWE
LDQM
I/O Control
512K x 32
512K x 32
512K x 32
512K x 32
Data Input Register
Bank Select
Row Decoder
Row Buffer
Refresh Counter
1
43
86
44
Summary of Contents for TH-V70
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