2-56(No.YA608<Rev.001>)
(No.YA608<Rev.001>)2-55
MPEG PWB ASS'Y (3/18)
[CI2000/CI2002]
HU-71200005
lt-19db9bd_mpeg-02_0520_2/21_0.0
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
All locations are from 1 to 39 in this page
Option for Free to Air
Option for CI
from CPU_OE
from Reset
to CPU_PIO
from CPU CLOCK
to CPU_WAIT
Control signal for host interfacing
from CPU_BE0
CI1_IRQ
CI1_TDI3
TO_D3
CI1_WAIT
CI1_TDI5
TO_D5
CI1_TDI1
TO_D1
CI1_MDI3
TO_CLK
CI1_MDI0
CI1_TDI6
CI1_MDI1
CI1_VLDO
TO_STR
CI1_CLKO
CI1_MDI4
CACLK
TO_D4
CI1_MDI2
CI1_CD2
TO_D6
TO_D7
CI1_MDI6
CI1_MDI5
CI1_TDI4
CI1_TDI7
CI1_TSTRI
CI1_STRO
CI1_TDI2
CI1_TVLDI
CI1_MDI7
CI1_TDI0
CI1_VLDI
TS_CLK
TS_STR
TS_VLD
CAD1
CAD7
CAD0
CAD5
CAD1
CAD7
CAD4
CAD5
CAD4
CAD6
CAD0
CAD3
CAD6
CAD2
CAD2
CASTR
CACLK
CAD3
CAVLD
CI1_STRI
CI1_CLKI
nRST
HOE
CPU_WAIT
CI_IRQ
CLK27M_CI
HWE
nCI2002_CS
CASTR
CAVLD
TO_VLD
DATA6
CI1_MDO1
CI1_MDO4
TS_DATA4
CI1_A11
TO_CLK
DATA0
DTACK
DATA3
CI1_A6
CAS1PWR
TO_D2
DATA7
DATA5
ADDR2
CI1_D5
TS_DATA6
CI1_A4
CI1_TDI3
CI1_A2
CI1_VLDO
CI1_D2
CI1_A0
CI1_A11
CI1_MDO1
TS_DATA6
CI1_CD1
TO_D1
DATA1
ADDR15
CI1_D5
CI1_D4
CI1_MDO7
CI1_MDO3
CI1_A8
CI1_TDI6
CI1_A5
CI1_A1
CI1_A0
TS_DATA7
ADDR15
CI1_A2
TS_VLD
CI1_D3
CI1_MDO5
TS_DATA3
CI1_MDO2
CI1_A7
CI1_CD2
CI1_A8
DATA4
nCI2002_CS
CI1_CE
CI1_D7
CI1_MDO3
TS_DATA5
ADDR16
DATA1
DATA2
CI1_A3
ADDR3
CI1_D6
CI1_MDO5
CI1_TCLKI
CI1_TDI7
CI1_TSTRI
CI1_D0
ADDR1
CI1_MDO4
CI1_D4
DATA5
TS_DATA2
TS_DATA1
CI1_TDI2
TS_DATA0
CI1_WE
TO_D7
CLK27M_CI
DATA0
CI1_A10
nDTACK
CI1_TDI5
CI1_TDI4
CI1_A4
TS_DATA3
TS_DATA1
CI_IRQ
TS_DATA7
DATA7
CI1_D0
CPU_WAIT
DATA2
ACK
HOE
HWE
ADDR3
CI1_OE
DATA4
CI1_A9
CI1_A5
CI1_D1
CI1_MDO0
CI1_D1
TO_D5
TO_D6
CI1_MDO6
CI1_A6
CI1_D7
CI1_A1
ADDR1
CI1_A3
TS_DATA5
TO_D3
DATA3
CI1_A10
nDTACK
TS_STR
TS_CLK
ADDR16
nRST
CI1_MDO6
CI1_D3
CI1_TCLKI
CI1_MDO2
CI1_D2
CI1_WAIT
TS_DATA2
TO_D0
TO_D4
TO_STR
ADDR2
CI1_D6
CI1_A7
TS_DATA0
CI1_MDO0
CI1_IRQ
CI1_IORD
DATA6
CI1_MDO7
TS_DATA4
CI1_TDI1
CI1_TDI0
CI1_STRO
CI1_IOWR
CAS1RST
CI1_A9
TO_VLD
CI1_CD1
CI1_CLKO
CI1_TVLDI
DTACK
CI1_IOWR
CAS1PWR
CI1_CE
CI1_OE
CI1_WE
CI1_IORD
CAS1RST
TO_D0
TO_D2
CI1_CD2
CACLK
CI1_CLKO
CI1_STRO
CI1_MDO[7..0]
CI1_VLDO
CAVLD
CI1_MDI[7..0]
CI1_STRI
CI1_VLDI
CI1_A[11..0]
CI1_WAIT
CI1_IRQ
CAD[7..0]
CASTR
TS_STR
TS_CLK
TS_VLD
CPU_WAIT
F_OE
CI_IRQ
nRST
CLK27M_CI
F_WE/DQM0
nCI2002_CS
TS_DATA[7..0]
CI1_CD1
CI1_CLKI
ADDR16
ADDR15
ADDR3
ADDR2
ADDR1
CI1_IORD
CAS1PWR
CAS1RST
CI1_OE
CI1_IOWR
CI1_CE
CI1_WE
+3V3
+5V
+3V3
+3V3
+3V3
+5V
+3V3
+3V3
+3V3
+5V
+3V3
PR4
OPEN-000*4
1
8
2
7
3
6
4
5
C1
104p/1005
R10
470/1005
CI2000PB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
TDO3_A
TDO4_A
TDO5_A
TDO6_A
TDO7_A
GND
ADDR10_B
/OE_B
/CE_B
D7_B
D6_B
D5_B
D4_B
D3_B
3.3V
D3_A
D4_A
D5_A
D6_A
D7_A
/CE_A
ADDR10_A
/OE_A
GND
27CLK
RESET
SEL1
SEL0
HA2
HA1
HA0
/HCE
/HWE
/HOE
/HIRQ
ACK
DTACK
HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
TO_CLK
TO_STR
TO_VLD
TO_D7
TO_D6
TO_D5
TO_D4
TO_D3
TO_D2
TO_D1
TO_D0
GND
CD1_B
CD2_B
/IORD_B
/IOWR_B
ADDR11_B
PWR_B
ADDR9_B
ADDR8_B
PWR_A
ADDR11_A
ADDR9_A
ADDR8_A
RESET_A
/IORD_A
/IOWR_A
/WE_B
/IRQ_B
+5V
/WE_A
/IRQ_A
CD1_A
CD2_A
ADDR7_A
TOA_STR
TOA_VLD
GND
TI_CLK
TI_STR
TI_VLD
TI_D0
TI_D1
TI_D2
TI_D3
TI_D4
TI_D5
TI_D6
TI_D7
D0_B
D1_B
D2_B
/WAIT_A
/WAIT_B
D0_A
D1_A
D2_A
RESET_B
+3.3V
ADDR7_B
ADDR6_B
ADDR5_B
ADDR4_B
ADDR3_B
ADDR2_B
ADDR1_B
ADDR0_B
GND
ADDR0_A
ADDR1_A
ADDR2_A
ADDR3_A
ADDR4_A
ADDR5_A
ADDR6_A
TDO3_B
TDO4_B
TDO5_B
TDO6_B
TDO7_B
TIA_STR
TIB_STR
TDI0_B
TDI1_B
TDI2_B
TDI3_B
+5V
TDI0_A
TDI1_A
TDI2_A
TDI3_A
GND
TDI4_A
TDI5_A
TDI6_A
TDI7_A
TIB_VLD
TIB_CLK
TOA_CLK
TIA_VLD
TIA_CLK
TDI4_B
TDI5_B
TDI6_B
TDI7_B
TOB_CLK
TOB_VLD
TOB_STR
TDO0_B
TDO1_B
TDO2_B
test
TDO2_A
TDO1_A
TDO0_A
R13
472/1005
L1
BLM18AG601SN1D
R5
R7
R16
472/1005
C2
104p/1005
R3
470/1005
R15
OPEN-000/1005
R17
OPEN-000/1005
C3
104p/1005
R9
470/1005
R2
OPEN-000
PR3
470*4
1
8
2
7
3
6
4
5
R1
000
PR2
470*4
1
8
2
7
3
6
4
5
R12
103/1005
C5
104p/1005
R18
000
R14
OPEN-472/1005
C4
104p/1005
PR6
470*4
1
8
2
7
3
6
4
5
U2
ELM7S04B
1
2
3
4
5
NC
A
GND
Y
VCC
R11
470/1005
R4
470/1005
PR1
OPEN-000*4
1
8
2
7
3
6
4
5
R8
OPEN-000/1005
OPEN-000/1005
OPEN-000/1005
PR5
470*4
1
8
2
7
3
6
4
5
R6
470/1005
R19
OPEN-000
CI1_D[7..0]
DATA[7..0]
U1
MPEG PWB(4/18)
MPEG PWB(9/18)
MPEG PWB(9/18)
MPEG PWB(10/18)
MPEG PWB(9/18)
MPEG PWB(9/18),(11/18)
MPEG PWB(9/18),(10/18)
MPEG PWB
(9/18),(11/18),(12/18)
MPEG PWB
(5/18)
MPEG PWB(9/18),(11/18),(12/18),(15/18)
MPEG PWB(9/18),(11/18),(12/18),(15/18)
MPEG PWB(4/18)
MPEG PWB(9/18)
MPEG
PWB
(4/18)
MPEG
PWB
(4/18)
MPEG PWB CIRCUIT DIAGRAM (3/18) [CI2000/CI2002]