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JVL Industri Elektronik A/S - User Manual - Ethernet for MAC and MIS motors
Note ! Changes will only become effective after reconfiguring and restarting the Ether-
CAT master!
Precautions
In a typical EtherCAT system the master will periodically send process data to all devices
on the network. Ideally, this process data will be received by the slave devices with a
fixed delay relative to the Sync0 signal.
For example, the master may configure the Sync0 period on all slaves to 1 millisecond,
and time its communications so that the slaves receive updated process data every milli-
second, exactly 50 microseconds before the Sync0 signal occurs.
It's very common in an EtherCAT system for the master to run on a complex PC oper-
ating system, and therefore not have the high degree of real time performance that the
slaves possess.
In such cases there can be a significant amount of timing jitter on the process data mes-
sages that the master sends. For example, if the master has +/- 100 microseconds of jit-
ter on its message transmission timing, then the slave may receive the process data
update anywhere from 150 microseconds before Sync0 to 50 microseconds after Sync0.
This can cause system level problems such as incorrect trajectory interpolation in cyclic
synchronous position mode.
Configuring the process data sync managers to use Sync0 synchronization mode can re-
solve the problems caused by timing jitter in the master. In this mode the master can
compensate for its worst case timing jitter by transmitting the process data to the slaves
sufficiently early to ensure that the data will be received before the Sync0 signal. The
slaves will not use the process data received until the Sync0 time, so system can remain
well synchronized even with a significant amount of timing jitter in the master.
For example, in a system with a cycle time of 1ms and +/-100 microseconds of timing
jitter on the master, the master could be configured to transmit its process data with a
300 microsecond offset (30% of the cycle time) from the Sync0 time on the slaves. This
would ensure that the slave devices receive the process data well clear of the Sync0 up-
date. Since the slaves are configured in Sync0 synchronization mode, they will not use the
updated process data until the Sync0 signal occurs.
Debugging synchronization (Only MAC modules)
The distributed clock and Sync0 signals are all generated internal to the slave devices on
the network. This can make it difficult to debug and verify the correct operation of the
system synchronization mechanisms. JVL EtherCAT MAC modules provide some useful
diagnostic capabilities that can aid the system developer in this area.
One extremely useful tool for debugging synchronization issues is to program a general
purpose module output pin to generate a pulse when the Sync0 signal occurs on the
drive. Using an oscilloscope, the Sync0 signals of multiple drives can thereby be viewed
directly. In a correctly configured system the Sync0 signals of all drives should occur si-
multaneously with no drift between them.
The function is enabled by issuing command 0x13 to the module command register. The
sync0 pulse is then present on the O1 output of the module. Disabling is done with the
Register 15 - Command register, page 231
for information
about the module command register, and chapter 2 for how to use the general module
I/O's.
Summary of Contents for MAC00-EC4
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