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JVL Industri Elektronik A/S - User Manual - Ethernet for MAC and MIS motors
8.3
Sercos Communication
8.3.1
Sercos
®
communication
The MAC00-ES4x Sercos
®
module and the MIS/MILxxxES Sercos
®
motor from JVL are
both equipped with two M12 Ethernet ports, enabling the possibility for line and ring
structures. The JVL Sercos
®
implementation is based upon the Sercos
®
International
specification v.1.1.2.
8.3.2
Drive synchronization
The MAC00-ES4x Sercos
®
module and the MIS/MILxxxES Sercos
®
motor use the FSP
Sync profile for synchronization of motors in the network. This is used by most masters
for their FSP Drive/Pack profile implementation. The sync profile is supported by the JVL
MAC00-ES4x module in MAC400-MAC4500 servo motors and by JVL MIS/MILxxxES
stepper motors with embedded Sercos
®
module.
8.3.3
Sercos
®
state machine
Figure
3:
Sercos®
communication
state
machine
Sercos
®
Communication between the master and the slaves is split into 6 phases (states).
Please refer to the state machine figure. From power-up and until the slave receives Ser-
cos
®
telegrams, the slave is in the NRT (Non-Real Time) state. Communication Phases
0 and 1 (CP0, CP1) identify the slaves on the net. In communication phase 2 (CP2) the
time and data structure of the protocols for phase 3 and 4 (CP3, CP4) are prepared and
the slaves are configured. At the transition to CP3 the slave parameter settings related
to the Sercos
®
profiles are checked for plausibility. In the event of an error, the switch
to CP3 is refused with an error message, and the slave remains in CP2. The phases are
run through in ascending order. It is only possibly to drop back a phase by way of CP0.
The communication phases are dictated by the master. When CP4 is reached, the initial-
ization is completed.
Only in the case of a communication error the slaves shall switch to NRT state. The com-
munication phases are indicated on the Sercos
®
status LED, in the front of the MAC mo-
tor Sercos
®
module, and on the back of the MIS/MIL motors.
TT3141-01GB
NRT state
CP3
CP0
CP1
CP2
CP4
Summary of Contents for MAC00-EC4
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