2600AS-901-01 Rev. B / September 2008
Return to
19-175
Series 2600A System SourceMeter® Instruments Reference Manual
Section 19: Remote Commands
status.operation.instrument.smuX.trigger_overrun.condition
status.operation.instrument.smuX.trigger_overrun.enable
status.operation.instrument.smuX.trigger_overrun.event
status.operation.instrument.smuX.trigger_overrun.ntr
status.operation.instrument.smuX.trigger_overrun.ptr
smuX = smua or smub
Attribute
Operation status SMU X trigger overrun register set.
Default
0
TSP-Link
accessibility
This attribute can be accessed from a remote TSP-Link node.
Usage
Reads condition, enable, event, NTR, and PTR registers:
operreg = status.operation.instrument.smuX.trigger_overrun.condition
operreg = status.operation.instrument.smuX.trigger_overrun.enable
operreg = status.operation.instrument.smuX.trigger_overrun.event
operreg = status.operation.instrument.smuX.trigger_overrun.ntr
operreg = status.operation.instrument.smuX.trigger_overrun.ptr
Writes to enable, NTR, and PTR registers:
status.operation.instrument.smuX.trigger_overrun.enable = operreg
status.operation.instrument.smuX.trigger_overrun.ntr = operreg
status.operation.instrument.smuX.trigger_overrun.ptr = operreg
Set
operreg
to one of the following values:
0
Clears all bits.
status.operation.instrument.smuX.trigger_overrun.ARM
Sets ARM bit (B1).
status.operation.instrument.smuX.trigger_overrun.SRC
Sets SRC bit (B2).
status.operation.instrument.smuX.trigger_overrun.MEAS
Sets MEAS bit (B3).
status.operation.instrument.smuX.trigger_overrun.ENDP
Sets ENDP bit (B4).
operreg
can also be set to the decimal weight of the bit to be set. Examples:
To set bit B1 (ARM), set
operreg
to 2 (2
1
).
To set bit B3 (MEAS), set
operreg
to 8 (2
3
).
To set bit B4 (ENDP), set
operreg
to 16 (2
4
).
To set more than one bit of the register, set
operreg
to the sum of their decimal weights. For
example, to set bits B1 and B4, set
operreg
to 18 (2 + 16).
Remarks
• These attributes are used to read or write to the operation status SMU X trigger overrun registers.
• Reading a status register returns a value. The binary equivalent of the returned value indicates
which register bits are set. The least significant bit of the binary number is bit 0, and the most
significant bit is bit 15.
• The used bits of the operation status SMU X trigger overrun registers are described as follows:
•
Bit B1, ARM
: Set bit indicates that the arm event detector of the SMU was already in the
detected state when the trigger was received.
•
Bit B2, SRC
: Set bit indicates that the source event detector of the SMU was already in the
detected state when the trigger was received.
•
Bit B3, MEAS
: Set bit indicates that the measure event detector of the SMU was already in the
detected state when the trigger was received.
•
Bit B4, ENDP
: Set bit indicates that the end pulse event detector of the SMU was already in
the detected state when the trigger was received.
Details
.