In this appendix:
Overview .................................................................................. E-1
Clearing registers ................................................................... E-13
Programming and reading registers ....................................... E-14
Status byte and service request (SRQ) .................................. E-15
Status register sets ................................................................. E-19
TSP-Link system status .......................................................... E-26
Overview
Each Keithley Instruments Model 2657A provides a number of status registers and queues that are
collectively referred to as the status model. Through manipulation and monitoring of these registers
and queues, you can view and control various instrument events. You can include commands in your
test program that can determine if a service request (SRQ) event has occurred and the cause of the
event.
The heart of the status model is the Status Byte Register. All status model registers and queues flow
into the Status Byte Register.
The entire status model is illustrated in the
(on page E-5).
Status register set contents
Typically, a status register set contains the following registers:
•
Condition
(
.condition
): A read-only register that is constantly updated to reflect the present
operating conditions of the instrument.
•
Enable Register
(
.enable
): A read-write register that allows a summary bit to be set when an
enabled event occurs.
•
Event Register
(
.event
): A read-only register that sets a bit to 1 when the applicable event
occurs. If the enable register bit for that event is also set, the summary bit of the register will set
to 1.
•
Negative Transition Register (NTR)
(
.ntr
): When a bit is set in this read-write register, it
enables a 1 to 0 change in the corresponding bit of the condition register to cause the
corresponding bit in the event register to be set.
•
Positive Transition Register (PTR)
(
.ptr
): When a bit is set in this read-write register, it
enables a 0 to 1 change in the corresponding bit of the condition register to cause the
corresponding bit in the event register to be set.
Appendix E
Status model
Summary of Contents for 2657A
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