Section 8
:
Status Model
Series 3700 System Switch/Multimeter Reference Manual
8-20
Document Number: 3700S-901-01 Rev. A / August 2007
Measurement event registers
The Series 3700 has one register set associated with measurement event status. As an
example, to set the buffer available bit:
status.measurement.enable = status.measurement.BAV
The bits used in the Measurement Event Registers are described as follows:
ROF:
Set bit indicates that an overflow reading has been detected.
BAV:
Set bit indicates that there is at least one reading stored a reading buffer.
INST:
Set bit indicates that a bit in the measurement instrument summary register is set.
Refer to the
status.measurement.*
(on page 9-187) ICL command for the attributes to control
and read the bits in the measurement event register.
Queues
The Series 3700 uses two queues, which are first-in, first-out (FIFO) queues:
Output queue
: Used to hold response messages.
Error queue
: Used to hold error and status messages.
The Series 3700 status model shows how the two queues are structured with the other
registers.
Output queue
The output queue holds data that pertains to the normal operation of the instrument. For
example, when a print command is sent, the response message is placed in the output queue.
When data is placed in the output queue, the message available (MAV) bit in the status byte
register sets. A response message is cleared from the output queue when it is read. The output
queue is considered cleared when it is empty. An empty output queue clears the MAV bit in the
status byte register. A message is read from the output queue by addressing the Series 3700 to
talk.
Error queue
The error queue holds error and status messages. When an error or status event occurs, a
message that defines the error or status is placed in the error queue. When a message is placed
in the error queue, the error available (EAV) bit in the status byte register is set. An error or
status message is cleared from the error queue when it is read. The error queue is considered
cleared when it is empty. An empty error queue clears the EAV bit in the status byte register.
