Model 4200A-SCS Pulse Card (PGU and PMU) User's Manual
Section 8: Testing flash memory
4200A-PMU-900-01 Rev. A December 2020
8-9
Endurance testing
Endurance testing stresses the DUT with a number of Erase waveform cycles, and then
periodically measures both the voltage threshold in the programmed state (VTP) and the voltage
threshold of the erased state (VTE). These tests to determine the lifetime of the DUT, based on the
number of Erase cycles withstood by the device before a certain amount of shift, or
degradation, in either the VTP or VTE. The endurance test is performed a set number of program and
erase cycles while periodically measuring V
T
for both the programmed and erased state.
The following figure shows typical degradation on a NOR cell for both VTP and VTE as the number of
applied program/erase cycles increases.
Figure 164: Example results of voltage threshold shift in an Endurance test on a NOR flash cell
Connections for endurance testing - no switch matrix
For a direct connect configuration, the minimum number of pulse channels is equal to the number of
DUT terminals that need to be simultaneously pulsed, including terminals that must change from
connected to disconnected, or open, states for either the program or erase condition.
The following connection configuration does not require a switch matrix. It provides four channels of
pulse and four SMUs to permit full characterization of single (non-array) NVM DUT. This connection
method is used for both the initial program/erase investigation and endurance testing of a
directly-connected DUT.
All interconnects on instrument chassis are white SMA cables. Cables from the instrument to device
are BNC coaxial. Use triaxial to BNC adapters if necessary to connect to probe manipulators.
