Service Information
5-11
Power-on safeguard
NOTE
The power-on safeguard circuit dis-
cussed below is actually located on the
digital board in the Model 7001/7002
mainframe.
A power-on safeguard circuit, made up of U114 (a D-type
f ip-f op) and associated components, ensures that relays do
not randomly energize on power-up and power-down. This
circuit disables all relays (all relays are open) during power-
up and power-down periods.
The PRESET line on the D-type f ip-f op is controlled by the
68302 microprocessor, while the CLK line of the D-type
f ip-f op is controlled by a port line on the 68302 processor.
The Q output of the f ip-f op drives each switch card relay
driver IC enable pin (U101-U105, pin 8).
When the 68302 microprocessor is in the reset mode, the
f ip-f op PRESET line is held low, and Q out immediately
goes high, disabling all relays (relay driver IC enable pins are
high, disabling the relays.) After the reset condition elapses
(
≈
200msec), PRESET goes high while Q out stays high.
When the f rst valid STROBE pulse occurs, a low logic level
is clocked into the D-type f ip-f op, setting Q out low and
enabling all relay drivers simultaneously. Note that Q out
stays low, (enabling relay drivers) until the 68302 processor
goes into a reset condition.
Troubleshooting
Troubleshooting equipment
Table 5-3 summarizes recommended equipment for trouble-
shooting the Model 7036.
Troubleshooting access
In order to gain access to the relay card top surface to mea-
sure voltages under actual operation conditions, perform the
following steps:
1. Disconnect the connector card from the relay card.
2. Remove the Model 7001/7002 cover.
3. Install the relay card in the CARD 1 slot location.
4. Turn on Model 7001/7002 power to measure voltages
(see following paragraph).
Table 5-3
Recommended troubleshooting equipment
Description
Manufacturer
and model
Application
Multimeter
Keithley 2000
Measure DC voltages
Oscilloscope TEK 2243
View logic waveforms