Principles of Operation
6-7
Figure 6-6
Typical matrix card logic block diagram
NEXT ADRS
CLK
IDDATA
RELAYDATA
BUFFER
ENABLE
SELECT
CLEAR ADRS
STROBE
12
8
RELAYDATA
SERIAL TO PARALLEL
RELAY DRIVERS
ENABLE
RELAYS
POWER ON
RESET
CLR
8KX8
EPROM
DATA
ADRS
12-BIT
COUNTER
CLOCK
CLEAR
PARALLEL TO
SERIAL
IN
CLOCK
OUT
CLOCK
CLOCK
IN
OUT
IDDATA
STROBE
n card-specific
CARDSEL
CLRADDR
NEXTADDR
CLK
IDDATA
D7
D6
D5
D4
D3
D2
D1
D0
Figure 6-7
IDDATA timing diagram
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