Keithley 708A Instruction Manual Download

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Principles of Operation

6-8

pins low and enabling the driver outputs. At this time, valid
relay control data has been sent to the cards and is present in
the latches of the driver chips. This action allows the relays
to be controlled by the transmitted relay data information.

NOTE

The STROBE signal can be high or low on
power-up since the outputs of U119
(74HCT374) on the mother board are un-
defined at power-on. Since the falling edge
on STROBE, after the output enable cir-
cuit times out, enables the relay driver out-
puts, the power-up software must set
STROBE low before the timeout. It then
pulses STROBE high after the relay driver
shift registers have been cleared.

A hold-off period (typically 470ms) is included in the safe-
guard circuit to guard against premature enabling of the
relays. The time constant of the hold-off period is determined
by an R-C network.

6.5

Display circuitry

Model 708A display circuitry includes components needed
to control the front panel annunciator LEDs, crosspoint
LEDs, and to read front panel switches.

The display circuitry is on the front panel control board and
mother board. See Figure 6-8 for a block diagram of the
display board and Figure 6-9 for a simplified schematic of
the display board interface on the mother board. The front
panel display is multiplexed as 12 columns for the card
columns and one column containing the discrete annunciator
LEDs TALK, LSTN, REM, COPY, and ERR. Display
segment assignments for the multiplexed columns are shown
in Table 6-1.

Relay control

The CLK, RELAYDATA, and IDDATA lines are bused to the
card slot on the backplane board. A separate card select sig-
nal is sent to the card to enable it for receiving RELAYDATA
and sending IDDATA. The microprocessor controls the card
select signals through U119 (74HCT374) on the mother
board, which is decoded as an output port on the micropro-
cessor bus.

The relays are controlled by the serial data transmitted via
the RELAYDATA lines. Bytes for each card are shifted seri-
ally into latches located in the relay drivers. The serial data
is fed in through the DATA lines under control of the CLK
signal. As data overflows one register, it is fed out the Q'S
line of that register to the next IC down the chain.

Once all the bytes have been shifted into the card in the
switching system, the STROBE line is set high to latch the
relay information into the Q outputs of the relay drivers, and
the appropriate relays are energized (assuming the driver
outputs are enabled). Logic convention is such that the cor-
responding relay driver output must be low to energize the
associated relay, while the output is high when the relay is
de-energized. The STROBE signal is received by all cards
regardless of the state of their respective card select lines.

Power-on safeguard

Each card has a power-on safeguard circuit to ensure that re-
lays do not randomly energize upon power-up. Two NAND
gates of a 74HCT00 are configured as an R-S flip-flop. On
power-up, the Q output of the flip-flop is set high, holding the
low true OEN (output enable) pins of the relay drivers high.
Hence, the driver outputs are disabled, and all relays remain
de-energized regardless of the relay data information present
at that time.

The falling edge of the first STROBE pulse that comes along
(to load relay data) clears the R-S flip-flop, setting the OEN

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