Principles of Operation
6-13
6.7
Master/slave circuitry
The master/slave interface is a closed loop of serial commu-
nication and bused control signals. Its control circuitry
resides on the mother board. See Figure 6-11 for a simplified
schematic.
Each switching system has a Master/Slave In connector and
a Master/Slave Out connector. Serial data is sent from the
TXDATA pin of the output connector to the RXDATA pin of
the input connector on the next switching matrix in the loop.
All other interface signals (M/S TRIGGER, ALLREADY
LPRESET, and LPSENSE) are common to input and output
connectors. The light pen signals LPRESET and LPSENSE
are described in paragraph 6.6.
HCT08
HCT00
HCT32
U128
U127
HCT08
U125
HCT244
HCT244
+5V
D
Q
Q
HCT74
U4
E
U19
RXDATA
ALLREADY
M/S TRIGGER
LPRESET
LPSENSE
MASTER/SLAVE
INTERFACE
MAS TE R /S LAVE
IN
MASTER/SLAVE
OUT
TXDATA
ALL R EADY
M/S TRIGGER
L PRESET
L PSENSE
+5V
U134
38
HCT244
U136
U107
68B50
ACIA
TXCL K
RX CLK
RXDATA
RTS
TXDATA
IRQ
TO
68B09
FIR Q
U108
63B21
P IA
P A1
P A0
U134
+5V
38
O.C.
M/S TRIGGE R
CA2
P A2
IMRE ADY
AL L RE ADY
S L AVE
CA1
TR IGGE R
IRQ
TO
68B09
IR Q
HCT157
U135
1Y
S
1I0
1I1
U136
HCT244
HCT244
U136
EXTERNAL
TRIGGER
BNC
894.89 kHz
K1 (Energized)
U128
Figure 6-11
Master/slave interface simplified schematic
6.7.1 Serial communication
Serial data communication is managed by U107 (68B50
ACIA) and automatic retransmit logic: a U127 NAND gate
used as an inverter, U128 AND gates, and U125 OR gate.
The RTS (low true) output of U107 controls the automatic
retransmission of serial data. Stand-alone and master units
assert RTS to gate the TXDATA output of U107 through an
AND gate and via U125 onto the TXDATA pin of the master/
slave interface. Relay K101 is energized when power is
applied to the Model 708A.
Slave units negate RTS except when responding to a request
by the master for setup or status information. A negated RTS
signal blocks the TXDATA signal at its corresponding U128
AND gate. Incoming serial data to the RXDATA input of
U107 is also routed through a U128 gate, the U125 OR gate,
and onto the master/slave TXDATA pin to effect the auto-
matic retransmission.
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