D-2
Return to
2600S-901-01 Rev. C / January 2008
Appendix D: Status Model
Series 2600 System SourceMeter® Instruments Reference Manual
Overview
The Keithley Instruments Series 2600 System SourceMeter
®
provides a number of status registers
and queues, allowing the operator to monitor and manipulate the various instrument events. The
status model is shown in
through
. The heart of the status model is the
Status Byte Register. This register can be read by the user's test program to determine if a service
request (SRQ) has occurred, and what event caused it.
Status byte and SRQ
The Status Byte Register receives the summary bits of five status register sets and two queues.
The register sets and queues monitor the various instrument events. When an enabled event
occurs, it sets a summary bit in the Status Byte Register. When a summary bit of the Status Byte is
set and its corresponding enable bit is set (as programmed by the user), the RQS/MSS bit will set
to indicate that an SRQ has occurred, and the GPIB SRQ line will be asserted.
Status register sets
A typical status register set is made up of a condition register, an event register and an event
enable register (many also have negative and positive transition registers). A condition register is
a read-only register that constantly updates to reflect the present operating conditions of the
instrument.
When an event occurs, the appropriate event register bit sets to 1. The bit remains latched to 1
until the register is reset. When an event register bit is set and its corresponding enable bit is set
(as programmed by the user), the output (summary) of the register will set to 1. This in turn sets
another bit in a lower-level register, and ultimately sets the summary bit of the Status Byte
Register.
Queues
The SourceMeter uses an Output Queue and an Error Queue. The response messages, such as
requested readings, are placed in the Output Queue. As various programming errors and status
messages occur, they are placed in the Error Queue. When a queue contains data, it sets the
appropriate summary bit of the Status Byte Register (EAV for the Error Queue; MAV for the Output
Queue).