Keysight 34951A, User Manual

10

Keysight 34951A User’s Guide

Each channel can also generate current between -20 mA and +20 mA at 

630 nA resolution. When outputting current the High Sense and Low Sense 

terminals

are not used and are opened. For protection, each channel incorporates 

a fuse that will open at greater than 20 mA. If an overload condition exists, the 

fuse will open, but no error or SRQ will be generated. To reset the fuse, remove 

the overload and wait a few minutes for the fuse to cool. 

Waveform (Trace) Mode

Using the internal waveform point storage, you can output provided sine, square, 

or ramp and triangle wave shapes, or define your own wave shape with up to 

512,000 points. The module can output points with a settling time of 40 

μ

s and a 

200 kHz point-to-point update rate. 
The on-board memory provides storage for you to create up to 32 voltage or 

current waveforms. You can apply a different waveform to each channel to output. 

Or you can apply the same waveform to more than one channel. For each channel 

you can designate the gain, frequency, and/or offset for its output. 
The waveforms are stored in volatile memory. Therefore, whenever power to the 

34980A is cycled, the volatile memory empties of data it has contained.
The waveform feature of the 34951A is not intended as a full-featured substitute 

for a function generator, but as a means of storing point-to-point updates. 

Clock In 

You can configure each DAC channel on the module to synchronize off either an 

internally-generated 20 MHz clock or the positive edge of an external 

user-supplied clock. 
An external clock must be less than 10 MHz or indeterminate behavior will result. 

Additionally, as the maximum point-to-point update rate of the DACs is 200 kHz, 

if you configure a DAC to run off an external clock, you will need to ensure that the 

correct clock divisor is also configured for that DAC. For example, if you supply a 

10 MHz external clock, the minimum clock divisor is 50 because the maximum 

update rate is 200 kHz. If a clock divisor less than the minimum is configured, 

indeterminate behavior will results. Thresholds for the Clock In are 5 V TTL 

tolerant.