62 Principles Of Operation
A low-level CV or CC signal is generated by the applicable status comparator (P/O U502) and returned to the secondary
processor to indicate that the corresponding mode, CV or CC, is in effect.
In CV mode, an OR gate diode (D652) conducts and the CV loop regulates the output voltage. A CV error amplifier (P/O
U621) compares the programmed voltage signal CVPROG to VMON which is the output signal from the V_DIF
amplifier(P/O U621). The range of VMON is 0 volts to +10 volts which corresponds to the zero-to-full-scale output voltage
of the supply. If the output voltage exceeds the programmed voltage the OR GATE signal goes low causing the output
voltage to decrease to the programmed value.
Conversely, if the output voltage is less than the programmed voltage, the OR GATE signal goes high causing the output
voltage to increase to the programmed value. An externally applied dc signal, VPROG, can be used to program the output
voltage. A 0 volt to -5 volt VP level produces a proportional zero-to-full-scale output voltage.
In CC mode, an OR gate diode (D651) conducts and the CC loop regulates the output voltage. A CC error amplifier (P/O
U620) compares the programmed voltage signal CCPROG to IMON which is the output signal of 2nd I_AMP (P/O U620).
The range of IMON is 0 volts to +10 volts which corresponds to the zero-to-full-scale output voltage of the supply. If the
output current exceeds the programmed current, the OR GATE signal goes low causing the output current to decrease to the
programmed value.
Conversely, if the output current is less than the programmed current, the OR GATE signal goes high causing the output
current to increase to the programmed value. An externally applied dc signal, IPROG, can be used to program the output
current. A 0 volt to -5 volt IP level produces a proportional zero-to-full-scale output current.
Switching/Downprogramming Control (P/O A10) These circuits include a Ramp Generator, Divider /Deadtime Latch, Fast
Sense Differential Amplifier, Pulse Width Modulator, Summing Comparator, Down-Programmer Control and OV
Comparator circuits.
The Divider/Deadtime Latch (U600, U601, U602) divides the 2-MHz ALE_CK signal from the Secondary
P and supplies
40 KHz pulses to the Ramp Generator (U607) and ON Latch ( U604).
The OR-GATE signal (CV or CC control signal as previously described) is summed with the 40 KHz triangular waveform
produced by the Ramp Generator. An input from the Fast Sense Differential Amplifier is also summed to compensate for a
sudden transient in the rectified output.
The width of the output pulses from the Summing Amplifier vary as the OR-GATE control signal increases or decreases.
These pulses are applied to the Pulse-Width Modulator (U603) via the On Latch. The PWM generates the square wave
pulses that are applied to the A3 FET assembly to turn the FET switches on and off. The Deadtime Latch resets the ON
Latch to provide a minimum off time for the FET switches.
The OV circuit compares the output voltage level with the OVREF signal which represents the programmed overvoltage
level. When the output voltage exceeds the programmed OV value, the downprogrammer circuits are activated and the FET
switches are turned off
The Downprogrammer control circuit generates control signal DP CONTROL whenever an OV or disable condition has
been detected, or when the output voltage exceeds the programmed value. DP CONTROL causes the downprogrammer
FETs (Q980, Q981) on the A9 Downprogrammer/Fast Sense board to conduct and conduct current away from the load.
A4 AC Input Board
The A4 Input Board contains the Inrush-Current Limit relay (K401), Main Power Relays (K402, K403), and
current-limiting resistors (R407, R408). On power-on, the current-limit relay (K401) closes allowing the dc rail capacitors
to charge under a controlled condition. This applies ac voltage to the A6 Bias Board. After the turn-on initialization period
(approximately 10 seconds), the main relays (K402, K403) close, shorting out the current-limit resistor.
Summary of Contents for 669 A Series
Page 2: ...Service Manual Keysight Series 669xA GPIB DC Power Supplies ...
Page 3: ......
Page 27: ......
Page 56: ...Troubleshooting 53 Figure 3 15 3 Inch Front Panel Frame Assembly ...
Page 57: ...54 Troubleshooting Figure 3 16 Assembly A10 Exploded View ...
Page 58: ...Troubleshooting 55 Figure 3 17 Assembly A10 Exploded View 6690A ...
Page 59: ...56 Troubleshooting Figure 3 18 Assembly A10 Exploded View 6691A 6692A ...
Page 60: ...Troubleshooting 57 Figure 3 19 Three Phase Line Choke Subchassis Wiring ...
Page 61: ...58 Troubleshooting Figure 3 20 24 Volt Fan Transformer ...
Page 77: ...74 Diagrams Figure 6 1 Test Point Waveforms for Table 6 3 sheet 2 of 2 ...
Page 79: ...Figure 6 3 A1 Front Panel Board Assembly Diagram ...
Page 81: ...Figure 6 5 A2 GPIB Board Component Location ...
Page 83: ...Figure 6 7 A3 FET Board Component and Test Point Location ...
Page 87: ...Figure 6 11 A4 AC Input Board Component and Test Point Location 12 9 10 11 ...
Page 89: ...Figure 6 13 A5 DC Rail Board Component and Test Point Location 13 14 ...
Page 91: ...Figure 6 15 A6 Bias Board Component and Test Point Location 15 16 17 18 19 19 20 22 ...
Page 94: ...Figure 6 17 Power Mesh Schematic Diagram All Models ...
Page 103: ......