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Keysight M809256PB OIF CEI-56G Rx Test Automation Application User Guide
5
OIF CEI-56G VSR PAM4 Tests
Single-lane Stressed Input Test
Overview
The Single-lane Stressed Input Test validates the ability of the host input
to tolerate the sinusoidal jitter with the specified limit. The test signal is
applied at TP4a using a Host Compliance Board (HCB).
Connection Diagram
For Single-lane tests, connect the instruments as shown in
Figure 49
Single Lane Stressed Input Test connections for VSR Host