Keysight M809256PB OIF CEI-56G Rx Test Automation Application User Guide
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OIF CEI-56G VSR PAM4 Tests
5
Multi-lane Stressed Input Test
Overview
The Multi-lane Stressed Input Test validates the ability of the host input to
tolerate the sinusoidal jitter with the specified limit. The test signal is
applied at TP4a using a Host Compliance Board (HCB).
Connection Diagram
For Multi-lane tests, connect the instruments as shown in
and
Figure 57
Multi Lane Stressed Input Test connections for VSR Host