COMe-bSL6 – User Guide Rev. 1.4
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Function
Second level Sub-Screen / Description
PCI Express
Configuration>
(continued)
PCI Root Port 1
(COMe PCIe#4)>
or
PCI Root Port 2
(COMe PCIe#5)>
or
PCI Root Port 3
(COMe PCIe#6)>
or
PCI Root Port 4
(COMe PCIe#7)>
or
PCI Root Port 9
(COMe PCIe#0)>
or
PCI Root Port 10
(COMe PCIe#1)>
or
PCI Root Port 11
(COMe PCIe#2)>
or
PCI Root Port 12
(COMe PCIe#3)
(continued)
PME SCI>
PCI Express PME SCI
[Enabled, Disabled]
Hot Plug>
PCI Express hot plug
[Enabled, Disabled]
Advanced Error
reporting>
Advanced –error reporting
[Enabled, Disabled]
PCIe Speed>
Configures PCIe speed
[Auto, Gen 1, Gen 2, Gen3]
Transmitter Half
Swing>
Transmitter half swing
[Enabled, Disabled]
Detector Timeout>
Number of mSeconds the reference code waits
for a link to exit detect state for enabled ports
before assuming there is no device and
potentially disabling the port.
Extra Bus
Reserved>
Extra bus reseved (0-7) for bridges behind this
root bridge.
[0]
Reserved Memory>
Reserved memory for this root bridge
Range: (1MB-20MB)
[10]
Reserved I/O>
Reserved IO for this root bridge
Range: (4 k, 8 k, 16 k, 20 k)
[4]
PCH PCIE1 LTR>
PCH PCIE latency reporting
[Enabled, Disabled]
Snoop latency
Override>
Snoop latency override or Non Snoop Override
for PCH PCIE.
Disabled: to disable override
Manual: to manually enter override values and
Auto (default): maintain default BIOS flow.
[Disabled, Manual, Auto]
Non Snoop latency
Override>
Force LTR
Override>
Force LTR override for PCH PCIE.
Disabled: LTR override not forced
Enable: LTR overrides values forced and LTR
messages from device are ignored.
[Enabled, Disabled]
PCIE1 LTR Lock>
PCIE LTR configuration lock
[Enabled, Disabled]
PCIE CLKREQ
Mapping Override>
PCIE CLKREQ Override for default platform
mapping
[Default, No CLKREQ, Custom number]
Extra Options>
Detect Non-
Compliance
Device>
Detects non-compliance PCI express device. If
enabled, It takes more time at post time.
[Enabled, Disabled]
