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CP6924-1-RA-A User Guide
33
3.4.2.5
J5 Connector
•
PICMG 2.16 Link Port 9 to Link Port 19 (10/100/1000Base-T)
3.5
Write Protection Feature
The CP6924 supports hardware driven write protection for all non-volatile memory devices. Depending on the device, the
protection is implemented either by a dedicated write protection signal, by disabling the write enable signal, or by the
whole interface.
Two levels of hardware write protection are supported: standard and enhanced. The protection level is set by a backplane
signal (EWP). It is located on connector J4, pin A9. If left open, the signal is inactive. If pulled to GND, the signal is active.
The following table shows how to configure the write protection. Default setting is 'standard'.
Table 3-8:
Connector J5 Pinout
Pin
Row A
Row B
Row C
Row D
Row E
Row F
22
FL_DA19-
GND
FL_DC19-
GND
21
FL_DB19-
GND
FL_DD19-
GND
20
FL_DA18-
GND
FL_DC18-
GND
19
FL_DB18-
GND
FL_DD18-
GND
18
FL_DA17-
GND
FL_DC17-
GND
17
FL_DB17-
GND
FL_DD17-
GND
16
FL_DA16-
GND
FL_DC16-
GND
15
FL_DB16-
GND
FL_DD16-
GND
14
FL_DA15-
GND
FL_DC15-
GND
13
FL_DB15-
GND
FL_DD15-
GND
12
FL_DA14-
GND
FL_DC14-
GND
11
FL_DB14-
GND
FL_DD14-
GND
10
FL_DA13-
GND
FL_DC13-
GND
9
FL_DB13-
GND
FL_DD13-
GND
8
FL_DA12-
GND
FL_DC12-
GND
7
FL_DB12-
GND
FL_DD12-
GND
6
FL_DA11-
GND
FL_DC11-
GND
5
FL_DB11-
GND
FL_DD11-
GND
4
FL_DA10-
GND
FL_DC10-
GND
3
FL_DB10-
GND
FL_DD10-
GND
2
FL_DA9-
GND
FL_DC9-
GND
1
FL_DB9-
GND
FL_DD9-
GND
EWP Signal
Write Protection Level
Inactive (3.3V or open)
Standard
Active (GND)
Enhanced
