L-Card L-502-P-G-D-I, User Manual

Page 1: ...UFACTURING DISTRIBUTION http en lcard ru en lcard ru Revision 1 1 0 October 2017 L 502 P G D I L 502 P G L 502 P G D L 502 X G L 502 X G D L 502 X X L 502 X X D Measuring voltage converters A family o...

Page 2: ...ard LLC 117105 Moscow Varshavskoye shosse 5 block 4 bld 2 tel 495 785 95 19 fax 495 785 95 14 Internet contacts http en lcard ru E Mail Sales department en lcard ru Technical support en lcard ru L 502...

Page 3: ...NC_IN SYNC_OUT is changed to START_IN START_OUT accordingly 05 2015 1 0 7 Added item 3 3 5 item 5 5 1 03 2016 1 0 8 Added Chapter 7 02 2017 1 0 9 Paragraph added 3 3 4 1 07 2017 1 0 10 A warning is ad...

Page 4: ...L 502 version number Module identification in a multi module configuration 17 2 5 Software installation 18 CHAPTER 3 THE DEVICE AND PRINCIPLE OF OPERATION L 502 19 3 1 Conventions 19 3 1 1 Convention...

Page 5: ...of possible problems 45 4 5 2 Conditions for correct connection and settings L 502 46 4 6 Calculation of the total load power of L 502 output circuits 48 CHAPTER 5 SPECIFICATIONS 49 5 1 ADC 49 5 1 1...

Page 6: ...mmon ground and differential 64 6 1 7 Connecting a power supply to the ADC input 65 6 1 8 Consistent connection of remote current sources or voltage through a long line with a wave resistance of Zw wi...

Page 7: ...he output resolution of the high and low byte asynchronous or synchronous data output mode with a frequency of up to 1 million words per second Processor Blackfin 530 MHz 32 MB RAM JTAG input optional...

Page 8: ...t 5 The synchronization cable is supplied separately The cable is used to connect two L 502 modules In the general case for the connection of N pcs of L 502 modules on one motherboard you will need N...

Page 9: ...5 1 25 0 6 10 5 2 5 1 25 0 6 0 3 0 15 0 07 ADC common mode signal range V 1 5 5 10 DAC range V output current mA 5 10 D 5 1 5 1 5 1 The word width of the module data bit 32 16 16 32 Multiple frequency...

Page 10: ...X9050 9030 PLX Tech PLX9050 9030 FPGA Altera Acex1K Indication on the panel Yes No No No The possibility of remote firmware update FPGA Yes No No Yes Program activation of pull up resistors of digital...

Page 11: ...he system unit along with the installed adjacent PCI Express modules 2 1 1 2 1 3 8 JTAG DAC1 DAC2 2 1 2 PCI Express X1 FPGA Cyclone IV Fig 1 2 L 502 version 3 face layout JTAG connector Internal signa...

Page 12: ...dden to connect Output resolution configuration connector s 2 1 3 Internal signal connector 8 digit serial number Backup boot configuration connector 2 1 1 Eternal signal connector Module name Intermo...

Page 13: ...layout 1 4 Documentation structure for L 502 A complete guide to the L 502 is divided into four separate books L 502 User Manual L 502 Programmer Manual L 502 Connexion samples L 502 Low level descri...

Page 14: ...mory This loading mode is considered the main mode and the L 502 always comes with a jumper set to contacts 1 2 No jumper FPGA is loaded with a backup copy of the firmware from Flash memory This loadi...

Page 15: ...he connector Jumper on 7 8 The contact DAC2 on the connector is connected to the DAC channel 2 Jumper on 7 9 The contact DAC2 on the connector is connected to 15V Jumper on 7 10 The contact DAC2 on th...

Page 16: ...e of this before installing the L 502 The design of the L 502 is in strict accordance with the requirements of the PCI Express specification But in the real case it is also important the quality of th...

Page 17: ...ycle The L 502 serial number is program accessible The first digit of the serial number corresponds to the version number of the product L 502 The product version is changed to improve the design and...

Page 18: ...ary drivers and libraries for Windows OS you must download and run the installer L Card L502 E502 SDK http www lcard ru download lpcie_setup exe For information on installing the driver and libraries...

Page 19: ...is constructive unit adopted in the ESKD module In particular we will start from this point by using the term multimodule synchronization 3 2 Introduction L 502 concept For the users who have already...

Page 20: ...impedances of signal sources and channel switching frequency In particular the advantage of L 502 on lower sub ranges of voltages of 0 5 V 0 2 V is gigantic with regard to L 7xx for the same applicat...

Page 21: ...have a galvanic isolation then all other L 502s lose their galvanic isolation in this scheme item 4 2 4 1 p 39 The L 502 has a 32 bit data word format in which besides the actual data for input or out...

Page 22: ...1 fref the period of the synchronization reference frequency tsw nsw fref the ADC channel commutation period within the frame equal to the sampling period of the ADC readouts where nsw can be specifie...

Page 23: ...ersonnel principle for acquiring ADC data 3 3 3 Digital input channel Synchronous digital input occurs with a period of tref ndin where ndin 1 2 2097152 is a configurable frequency division factor for...

Page 24: ...s contain the corresponding frequency dividers fref We list all possible options for user settings related to the selection of sources of reference frequency signals The internal generator 2 0 1 5 MHz...

Page 25: ...YN2 DAC2 DO1 DO16 DAC1 C X1 X16 Y1 Y16 GND32 2 0 1 5 I II Fig 3 2 L 502 synchronization system structure 3 3 5 2 Secondary synchronization The functionality of the secondary synchronization is embedde...

Page 26: ...hannel switch up to synchronization frequency frame size and interframe delay But with L 502 this principle is developed for better adaptation to the output physical properties of the signal source Fu...

Page 27: ...ing the data Accordingly nsu nsw nav means how many ADC counts from the beginning of the switching cycle of the given channel will be discarded or how many periods tref will be used to set the signal...

Page 28: ...quisition tasks where the magnitude of the relative signal delay between the ADC channels is important for measuring relative phase delays For this class of problems the theoretical calculated latency...

Page 29: ...elays in the ADC channel are given for the operating mode without averaging the data and without allocating additional cycles of the ADC for setting the signal Description Desig nation Timing sample M...

Page 30: ...f data collection tST_SU 45 ns Hold time of state 1 to START_OUT after the front CONV_OUT termination of data collection tST_H 150 ns The time to set the data at the DI input tDI_SU 5 ns Data hold tim...

Page 31: ...ount of Flash memory is provided for user tasks The L 502 I O subsystem includes nodes for the channel switch ADC DAC L 502 D digital I O and primary synchronization circuit 3 3 5 The galvanic isolati...

Page 32: ...of the computer starts initializing the devices the L 502 will download the firmware to the FPGA from Flash memory fig 3 5 and the L 502 internal power supply system will be fully turned on In this c...

Page 33: ...galvanic isolation the GND circuit has an internal connection point with DGND which in turn is connected to AGND In L 502 G with galvanic isolation DGND AGND circuits are isolated from GND and all oth...

Page 34: ...voltage input 1 16 for differential and common ground mode Operation voltage range 10 V see the details in section 4 4 p 44 Unused inputs X 1 16 are recommended to be connected to AGND or the correspo...

Page 35: ...g ground GND32 AGND Input In the with common ground mode common inverting channel input 1 32 For all modes must be connected to AGND in differential mode to increase noise immunity In the common groun...

Page 36: ...7xx m or AC 7xx f cable with the use of an additional adjacent crate slot in the PC system unit 39 40 1 2 3 4 5 7 9 11 13 15 6 8 10 12 14 16 17 19 18 20 21 23 22 24 25 27 26 28 29 31 30 32 DO15 DO13...

Page 37: ...common wire circuit for digital inputs and outputs DI_SYN2 DGND Input output Input Sync input 2 which can also act as an additional input to the digital input Compatible with the output logic level o...

Page 38: ...connection of digital lines three buses of 8 bits each With the addition of two additional universal inputs DI_SYN1 DI_SYN2 we get an almost important case of implementing interfaces with different de...

Page 39: ...DGND Common wire circuit for sync connector All digital signals on the synchronization connector correspond to the LVCMOS voltage level standard for 3 3V supply voltage The internal resistance of the...

Page 40: ...ecting N pcs of L 502 modules on one motherboard you will need N 1 pcs of synchronization cables If at least one L 502 in this connection scheme does not have galvanic isolation then the entire system...

Page 41: ...fin software on the L 502 board you should use one of the JTAG emulators from Analog Devices ADZS USB ICE ADZS HPUSB ICE or ADZS ICE 100B with the USB interface They differ significantly with USB tran...

Page 42: ...er is not exceeded see section 4 6 SC is not permitted Inputs DI_SYN1 DI_SYN2 10 V relative to the DGND circuit with an internal input resistance of at least 1 k Digital inputs DI1 DI16 From 0 4 to 6...

Page 43: ...tage rise rate between galvanically isolated circuits in L 502 G 10 kV s The maximum permissible circuit modes of the JTAG connector are not considered since the JTAG designated area is strictly limit...

Page 44: ...ances of the wires through which the through currents can flow with the connection of different devices or other external electrical causes inducing the parasitic offset voltage UYi UYj UGND are indic...

Page 45: ...oor result Why What do you need to consider If you answer below these questions links to the Internet resources of the site en lcard ru will be used 4 5 1 The physical causes of possible problems Phys...

Page 46: ...10 5 The AGND L 502 circuit must be connected to the common circuit of the signal source if there are several signal sources to the common junction of the common signal source wires 6 If you need to c...

Page 47: ...Optimizing the nsu and nav settings for the common ground mode is required Do not make common ground connections through the cable if there are no low resistance pull up resistors on the L 502 side 1...

Page 48: ...the DAC outputs power load taken from the output of 15 V power load taken from the output of 15 V power load taken from the output of 3 3 V In turn the power summands of the corresponding i th output...

Page 49: ...4 Voltages at the input Yi with regard to AGND for the differential measurement mode on the subbands 10 V 5 V The average value of the voltage at the inputs X and Y for the differential mode on the me...

Page 50: ...uring the AC voltage Frequency range of input signal kHz Limits of the permissible relative basic error of measuring the AC voltage from 0 01 to 50 incl 1 02 0 15 0 X X AC more than 50 to 100 incl 1 0...

Page 51: ...l applied to the ADC input V 2000 1 309 157 50 37 22 18 400 5 127 56 28 16 12 8 50 20 62 27 13 8 6 4 10 128 40 25 12 7 5 4 5 1 3 ADC inter channel passing Signal source resistance in the channel where...

Page 52: ...oducing DC voltage 0 3 Maximum allowable output current1 20 mA AC voltage playback range From 1 mV to 3 5 V AC voltage playback error According to section 5 2 1 5 2 1 AC voltage playback error Output...

Page 53: ...mode The actual speed depends on many factors of the software and hardware environment Maximum permissible input voltage range at the inputs DI1 DI16 at the inputs DI_SYN1 DI_SYN2 0 5 6 5 V 10 10 V Re...

Page 54: ...cal unit Output logic elements with a supply voltage of 3 3 V Output resistance typical value 110 Ohm Maximum leakage current in operating mode in high impedance state 1 A High impedance state with po...

Page 55: ...d 2 outputs to the slave 5 6 Characteristics of standard interfaces Parameter characteristics Value description Interface with a computer Standard for an interface with a computer PCIe x1 The bit dept...

Page 56: ...ge of galvanic isolation 500 V during 1 min The maximum permissible voltage rise rate between galvanically isolated circuits in L 502 G 10 kV s Total load power taken from all outputs L 502 The method...

Page 57: ...2 module AGND DGND3 GND DGND L 502 without galvanic isolation GND AGND L 502 without galvanic isolation 100 mA 100 mA 100 mA Maximum permissible through currents along AGND AGND AGND DGND DGND DGND ci...

Page 58: ...0 air pressure kPa from 84 to 106 5 9 2 Operating conditions Parameter Value For stability under climatic influences the converters in addition to the versions with the letter index I correspond to GO...

Page 59: ...icular case If necessary please contact en lcard ru or in the conference on the site en lcard ru 6 1 ADC entry point connection 6 1 1 Connecting to the ADC entry point of single phase voltage source 6...

Page 60: ...6 Integrating circuit Differential mode R1 R2 L 502 AGND GND32 X1 X2 X16 Y1 Y16 R1 R2 L 502 AGND X1 X2 X16 Y1 Y2 Y16 The transmission coefficient of the voltage in the frequency band is R2 R1 R2 If m...

Page 61: ...ry point The transmission coefficient of the voltage in the passband is R2 R1 R2 L 502 AGND GND32 X1 X2 X16 Y1 Y16 L 502 AGND X1 X2 X16 Y1 Y2 Y16 Can not be connected like this 6 1 1 11 Inductive pick...

Page 62: ...he following condition should be met R1 R2 50 if the switching frequency is maximal Allocate R1 R2 close to L 502 entry Only for voltage subbands 2 V 1 V 0 5 V 0 2 V R1 L 502 AGND X1 X2 X16 Y1 Y2 Y16...

Page 63: ...D X1 X2 X16 Y1 Y2 Y16 R2 R3 L Locate R1 close to L 502 input Only for voltage subranges of L 502 2 V 1 V 0 5 V 0 2 V 6 1 3 Connection to the ADC input for the case where the common wire of the signal...

Page 64: ...cuit In multichannel mode the equivalent impedance referred to the ADC input must be active It is necessary that R2 should not be more than 50 ohms if the switching frequency is maximal See limitation...

Page 65: ...lti channel mode at the maximum switching frequency 6 1 7 3 Differential mode offset potential due to current source in regard to AGND 6 1 7 4 Differential mode isolated current source Y1 X2 X16 R I L...

Page 66: ...correspond to one way matching of the long line on the side of the signal receiver 6 1 8 1 Mode with common ground 6 1 8 2 Differential mode R Z L 502 AGND GND32 X1 X2 X16 Y1 Y16 Z Y1 Y2 Y16 L 502 AGN...

Page 67: ...impedance of the signal source R balancing resistor on the signal source side The cable must be paired shielded twisted pairs with wave resistance of wire pairs Zw Below is a practical case where a b...

Page 68: ...2 must be preconfigured with jumper see section 2 1 2 on p 15 6 2 1 2 channel output 5 V 6 2 2 Single channel differential output 10 V L 502 D DAC1 DAC2 AGND R 1 5 5 DAC1 DAC2 AGND R 10 5 5 L 502 D Th...

Page 69: ...Connecting a contact to a digital input 6 3 3 1 Option 1 6 3 3 2 Option 2 3 3V R1 DI 1 16 AGND K1 L 502 DI_SYN1 2 A logical unit corresponds to an open contact The recommended resistor R1 nominal is...

Page 70: ...nchronization input DI_SYN1 GND DI_SYN2 L 502 The digital inputs DI_SYN1 2 which can be used as synchronization inputs are adapted to directly connect the optron output The internal pull up resistor o...

Page 71: ...71 Chapter 7 Dimensional drawing The dimensions are in millimeters...

Page 72: ...t 42 Table 4 5Maximum permissible through current by GND AGND DGND 42 List of figures Fig 1 1 Symbol system for L 502 module 7 Fig 1 2 L 502 version 3 face layout 11 Fig 1 3 L 502 version 1 or 2 face...

Page 73: ...73 Fig 4 7 The scheme of multi module synchronization of three L 502 version 3 top view of the computer s motherboard 40 Fig 4 8 Intermodule synchronization cable L 502 SYNC 41 Fig 4 9 JTAG 41...