Laird MSD45N
Hardware Integration Guide, version 1.1
Embedded Wireless Solutions Support Center:
http://ews-support.lairdtech.com
www.lairdtech.com/wireless
14
Laird Technologies
Americas: +1-800-492-2320 Option 2
Europe: +44-1628-858-940
Hong Kong: +852-2268-6567 x026
Integration Considerations
The following Wi-Fi information should be taken into consideration when integrating the MSD45N.
Series resistors are recommended in all six SDIO lines (27-56 ohms typically):
SDIO_CLK
SDIO_CMD
SDIO_DATA_0
SDIO_DATA_1
SDIO_DATA_2
SDIO_DATA_3
Also note the following:
Rout the SDIO bus as short and as similar in length as possible.
Keep the clock trace separate from other signal traces.
Note: Although these values may vary with the properties of your host interface and the PCB, they
are a reasonable starting point.
Note: The series resistors in the SDIO bus provide several design benefits:
If a host controller has too high of a drive strength, then bus ringing may result. Series
resistors can reduce this ringing on the I/O lines.
Adding 27-56 ohms of series resistance on the SDIO bus will reduce sharp transitional
edges, which may reduce EMI.
Having the series resistors in the PCB layout allows for design flexibility; if they are later
found to be unnecessary, zero (0) ohm jumpers may be used in their place.
Notes: No pull-up is required on the CLK line.
Make sure to apply the proper voltage on the VDD_IO input to the SiP to match the
signalling voltage of the SDIO host interface (1.8V or 3.3V typically, but it can be
anything in between these values).
The SDIO host must wait a minimum of 5
µ
sec before initiating access to the MSD45N
after VCC3_3 ramps up and settles
