Lanner electronics IAC-H670 Series, User Manual

 
Chapter3 BIOS Setup 

30 

User’s Manual 

SDRAM Timing by SPD: 

Selects whether DRAM timing is controlled by the SPD (Serial Presence Detect) 

EEPROM on the DRAM module. Setting to SPD enables CAS# Latency. RAS# Precharge, RAS# to CAS# 
Delay and Precharge Delay automatically to be determined by BIOS based on the configurations on the SPD. 

Selecting Manual allows users to configure these fields manually. 
 

DRAM Refresh:

 This option specifies the refresh rate frequency for the installed system memory SDRAM 

DIMMs. If you have good quality of DRAM, you can choose longer refresh rate to get better system 
performance. 

DRAM Cycle time (SCLKs):

 Select the number of SCLKs for an access cycle. The setting are:5/7 and 7/9.

 
CAS# Latency (SCLKs):

 This controls the timing delay (in clock cycles) before SDRAM starts a read 

command after receiving it. Settings are 3 Clocks and 2 Clocks. 2 Clocks increases the system performance 
while 3 Clocks provides more stable performance. 
 

SDRAM RAS# to CAS# Delay (SCLKs):

 This field allows you to set the number of cycles for a timing 

delay between the CAS ans RAS strobe signals, used when DRAM is written to , read from or refreshed. Fast 

speed offers faster performance while slow speed offers more stable performance. Settings: 3 Clocks and 2 
Clocks. 
 

SDRAM RAS# Precharge (SCLKs):

 The field specifies the idle cycles before precharging an idle bank. 

Settings: 7 Clocks, 6 Clocks and 5 Clocks. 

 
Internal Graphics Mode Select: 

This setting allows the Internal Graphics mode to be modified. The 

Optimal and Fail-Safe default settings is Enabled, 1MB. 

Option Description 

Enabled, 1MB 

This option allows the Internal Graphic controller to allocate 1MB of system 

memory for video display use. This is the default setting. 

Enabled, 512KB  This option allows the Internal Graphic controller to allocate 512KB of 

system memory for video display use. 

Disabled 

This option allocates no system memory for video display use. 

Display Cache Window Size: 

This setting allows the Display Cache Window Size to be modified. The 

Optimal and Fail-Safe default settings is 64MB. 

Option Description 

32MB 

This option allows caching of up to 32MB. 

64MB 

This option allows caching of up to 64MB. This is the default setting. 

AGP Aperture Window:

The field selects the size of the Accelerated Graphics Port( AGP) aperture. 

Aperture is a portion of the PCI memory address range dedicated for graphics memory address space. Host 

cycles that hit the aperture range are forwarded to the AGP without any translation. Settings are 4MB, 8MB, 
16MB, 32MB, 64MB, 128MB and 256MB. 
 

Initialize Display Cache Memory: 

This option will enabled or disable Local Memory (Display Cache) and 

UMA capable. Setting are Enabled and Disabled. 

 
Paging Mode Control: 

Display cache paging mode. Setting are Open and Closed. 

 
RAS-to-CAS: 

This field allows you to set the number of cycles for a timing delay between the CAS and 

RAS  strobe  signals,  used  when  DRAM  is  written  to  ,  read  from  or  refreshed.  Fast  speed  offers  faster 

performance while slow speed offers more stable performance. 

CAS Latency: 

This controls the timing delay before SDRAM starts a read command after receiving it. 

 
RAS Timing: 

This item controls the timing for RAS. Settings are Fast and Slow. 

 
RAS Precharge Timing: 

This item controls the number of cycles for RAS to be allowed to precharge.